Abstract: Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated.

Abstract: Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated.

Abstract: A test circuit within an existing design to enable the test circuit to test directly within the circuit. This invention provides a way to test and measure the leakage of the PLL loop filter capacitor leakage during test with a simple digital tester using existing pins. The test PLL circuit has circuit a plurality of capacitors and responsive amplifiers circuits for measuring leakage including a first capacitor set having multiple transistors coupled in series and with a reference resistor circuit coupled to a first amplifier and a second capacitor set having multiple transistors coupled in series and said reference resistor circuit coupled to a second amplifier to measure the leaking across the respective capacitors coupled to said first and second amplifiers and to provide an output of the leakage for measurement with the output of said first and second amplifiers.

Abstract: An exemplary embodiment of the invention is a method for evaluating jitter of a phase locked loop circuit generating a phase locked loop output signal. The method includes generating a test initiate signal and generating a trigger signal in response to the test initiate signal. The trigger signal is synchronized with the phase locked loop output signal. A disturbance signal is generated to induce jitter in the phase locked loop output signal. The jitter in the phase locked loop output signal is then evaluated.

Abstract: A tunable constant current source having temperature and power supply compensation is provided. The tunable constant current source includes a voltage regulator, a differential amplifier, a current source and a compensating load. The voltage regulator provides a substantially constant bias voltage VB. The differential amplifier receives the bias voltage VB and maintains a load voltage VL substantially equal to the bias voltage VB by way of a negative feedback. The current source generates a substantially constant current IREF from the differential amplifier. The compensating load varies with temperature changes to maintain the current IREF substantially constant, whereby the tunable constant current source may operate in a supply voltage range between about 0.5 volts to about 1.8 volts.