Abstract: The present invention provides a frequency-sampling circuit and method for characterizing a health condition of a test unit attached to a power supply. The frequency-sampling circuit is connected externally to the test unit. The circuit comprises an inductor and a capacitor connected in series at an output. When switched, the circuit resonates with an AC loop current to produce a damped-frequency response at the output. Frequency measurements of this response are processed to generate SoH or RUL estimates for the test unit. The voltages applied within the frequency-sampling circuit are limited, which in turn limits the AC loop current to avoid loading the power supply. Incorporating the inductance and capacitance with in the frequency-sampling circuit allows the circuit to be configured for different classes of test units having a wide range of characteristic impedances.

Abstract: The solder-joint integrity of digital electronic packages, such as FPGAs or microcontrollers that have internally connected input/output buffers, is evaluated by applying a time-varying voltage through one or more solder-joint networks to charge a charge-storage component. Each network includes an I/O buffer on the die in the package and a solder-joint connection, typically one or more such connections inside the package and between the package and a board. The time constant for charging the component is proportional to the resistance of the solder-joint network, hence the voltage across the charge-storage component is a measurement of the integrity of the solder-joint network.

Abstract: The system includes a current injection device in electrical communication with the switch mode power supply. The current injection device is positioned to alter the initial, non-zero load current when activated. A prognostic control is in communication with the current injection device, controlling activation of the current injection device. A frequency detector is positioned to receive an output signal from the switch mode power supply and is able to count cycles in a sinusoidal wave within the output signal. An output device is in communication with the frequency detector. The output device outputs a result of the counted cycles, which are indicative of damage to an a remaining useful life of the switch mode power supply.

Abstract: The solder-joint integrity of digital electronic packages, such as FPGAs or microcontrollers that have internally connected input/output buffers, is evaluated by applying a time-varying voltage through one or more solder-joint networks to charge a charge-storage component. Each network includes an I/O buffer on the die in the package and a solder-joint connection, typically one or more such connections inside the package and between the package and a board. The time constant for charging the component is proportional to the resistance of the solder-joint network, hence the voltage across the charge-storage component is a measurement of the integrity of the solder-joint network.

Abstract: The solder-joint integrity of digital electronic packages, such as FPGAs or microcontrollers that have internally connected input/output buffers, is evaluated by applying a time-varying voltage through one or more solder-joint networks to charge a charge-storage component. Each network includes an I/O buffer on the die in the package and a solder-joint connection, typically one or more such connections inside the package and between the package and a board. The time constant for charging the component is proportional to the resistance of the solder-joint network, hence the voltage across the charge-storage component is a measurement of the integrity of the solder-joint network.

Abstract: A low power circuit and method for detects in-situ failures or precursors to failures in solder-joint networks on actual operational devices and packages in the field. An amplifying detector such as provided by a common-gate transistor sources current to the network to generate a signal voltage and a reference voltage that is sensitive to the low voltage applied to the other side of the network. Generation of this self-adjusting reference voltage makes the detection circuit insensitive to the network low-voltage. Additional power savings and performance gains can be provided with the addition of a differential amplifier to set a fixed bias point and a level shifter to cancel noise. The detected failure or precursor of a selected monitor solder-joint network(s) is an indicator of the integrity of other operational solder-joint networks in the package, on the PWB or between PWBs.

Abstract: The system includes a current injection device in electrical communication with the switch mode power supply. The current injection device is positioned to alter the initial, non-zero load current when activated. A prognostic control is in communication with the current injection device, controlling activation of the current injection device. A frequency detector is positioned to receive an output signal from the switch mode power supply and is able to count cycles in a sinusoidal wave within the output signal. An output device is in communication with the frequency detector. The output device outputs a result of the dounted cycles, which are indicative of damage to an a remaining useful life of the switch mode power supply.

Abstract: A solder-joint detection circuit uses a resistive bridge and a differential detector to detect faults in the solder-joint network both inside and outside the digital electronic package during operation. The resistive bridge is preferably coupled to a high supply voltage used to power the package. Resistors R1 and R2 are connected in series at a first junction between the high and low supply voltages and a resistor R3 is coupled to the high supply voltage and connected in series with the resistance of the solder-network at a second junction. The network is held at a low voltage on the die. The detector compares the sensitivity and detection voltages and outputs a Pass/Fail signal for the solder-joint network.

Abstract: Text and graphics are justified along one physical dimension to a predetermined line of justification. A plurality of physical parameters are employed in the justification, each of the parameters is assigned a compression and an expansion adjustment ratio. Such ratios define the maximum adjustment range of each of the parameters. A priority of adjustment is assigned to each of the parameters such that one parameter being adjusted and capable of meeting justification needs is adjusted to the exclusion of all other possible parameter adjustments. In vertical justification of a plurality of columns, text distribution precedes the vertical adjustment. For such vertical justification, the priority of adjustment is based upon natural text/graphics breaks; top priority is use of lead outs, second is skips, third is spaces and last is textual adjustments. Justification is preferably proportional, i.e., the ratios are adjusted when the maximum permitted adjustment is not required for justification.

Abstract: Text and graphics are recursively (includes iteratively) distributed among a set of balanceable columns capable of receiving text and graphics. The recursive distributions are at successively varying columnar depths (all columns in each recursion have a common target depth), upon completing each recursion, the difference between the resulting shortest and longest column depths is measured and compared with a standard. If the standard is met, the distribution is made final, otherwise subsequent recursions up to a predetermined number of recursions are employed. If the standard is not met, then after the predetermined number of recursions, the distribution yielding the least differential is selected as the final distribution. Vertical justification of the columns follows.

Abstract: Machine-implemented text/graphics formatting is based upon a logical page area on a presentation-receiving medium, such as a CRT face, sheet of paper and the like. Named text and graphics receiving areas are selectively assignable to the logical pages of a document being formatted for visual presentation and are addressable and formattable independent of other formatting in any logical page. The named areas are machine defined such that one area can have portions thereof automatically assigned to and presented with any arbitrary number of logical pages. Such areas are managed in a text formatting machine to facilitate formatting headers based upon text contained in a succession of logical pages that are outside the named area. A first class of such named areas is placed upon the page when formatting to the page is ended, while a second class of such named areas is placed on the page in response to a command. The placement of the second class on a page can result in starting formatting new pages.