Abstract: A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.

Abstract: A system and method for semiconductor identification chip read out is presented. A user uses a stand-alone handheld device to extract product data, which includes manufacturing process attributes, from a semiconductor device. The semiconductor device couples to the hand held device through a subset of pins, such as a power pin, a ground pin, a clock in pin, and a data out pin. When coupled, the handheld device provides a clock signal to the semiconductor device. In turn, on chip logic within the semiconductor device detects the clock signal and gathers internal product data. Once gathered, the on chip logic provides the product data to the hand held device through the data out pin for a user to view. As a result, the user may track semiconductor devices more efficiently.

Abstract: A system and method for semiconductor identification chip read out is presented. A user uses a stand-alone handheld device to extract product data, which includes manufacturing process attributes, from a semiconductor device. The semiconductor device couples to the hand held device through a subset of pins, such as a power pin, a ground pin, a clock in pin, and a data out pin. When coupled, the handheld device provides a clock signal to the semiconductor device. In turn, on chip logic within the semiconductor device detects the clock signal and gathers internal product data. Once gathered, the on chip logic provides the product data to the hand held device through the data out pin for a user to view. As a result, the user may track semiconductor devices more efficiently.

Abstract: A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.

Abstract: A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.

Abstract: A method, system, and computer-usable medium for implementing a programmable DMA master with date checking utilizing a drone system controller. According to a preferred embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.

Abstract: A system and method for implementing a new protocol that uses new data structures in order to improve the performance of a token ring without changing its topology or degrading its fairness. A primary sender sends a data frame containing a data field addressed to a primary receiver. The protocol allows the primary receiver to enter "transmit mode" and assume another role as a secondary sender when the data frame is received and copied. The secondary sender overwrites the data field. Then, the secondary sender designates a secondary receiver to receive the update data and sends an acknowledgement message back to the primary sender to indicate that it has received data. The secondary receiver sends an acknowledgement to the secondary sender when the secondary transmission data is received. The primary sender checks for an acknowledgement from the primary receiver when the data frame returns. Then the primary sender transmits the data frame downstream.

Abstract: A method and system for increasing performance on a standard dual ring token ring by generating one or more sub-tokens so that multiple data transmissions can occur concurrently. Upon receipt of a data frame from the token holder, interface logic enables a receiver to generate a sub-token frame. The sub-token is used to notify the next downstream station that it may transmit data frames to other downstream stations. In this way, a second data transmission path can be established between downstream stations. In a similar manner, the receiver of a data frame sent by a sub-token owner will generate a sub-token frame for use by the next downstream station when its data arrives. Each sub-token is used to create a new sub-ring, thus allowing for concurrent data transmissions. Each new sub-ring must obey token ring protocol to avoid data collisions.

Abstract: An improved DES unit internally checks whether the DES algorithm is being performed without error. A standard DES algorithm performs an initial permutation of input data and then multiple rounds or iterations of the following: expanding part of a result of the initial permutation for the first iteration and a result of the previous iteration for the subsequent iterations, exclusive ORing a result of the expansion with key bits, performing a selection function on a result of the exclusive ORing, permuting a result of the selection function, and exclusive ORing a result of the permuting. In the improved DES unit, data check bits that correspond to the input data which has been expanded are exclusive NORed with key check bits that correspond to the key, and a result of the exclusive NORing is checked against a result of the exclusive ORing to identify any errors in the operation of the basic DES unit. Also, a check selection function is performed on the result of the exclusive ORing.

Abstract: A system translates a first group of cipher blocks based on a first encryption key to a second group of respective cipher blocks based on a second encryption key. Respective cipher blocks of the first and second groups represent the same data. The system comprises decryption hardware for sequentially decrypting the cipher blocks of the first group based on the first key. Encryption hardware is coupled to receive decrypted blocks output from the decryption hardware and sequentially encrypts the decrypted blocks into respective cipher blocks of the second group based on the second encryption key. A control unit controls the encryption hardware to encrypt the decrypted blocks into the respective cipher blocks of the second group while the decryption hardware decrypts cipher blocks of the first group. Consequently, decryption and encryption operations occur in parallel and the translation process is expedited.

Abstract: ANSI X3.92 Data Encryption algorithm is public knowledge, and is widely used where data security and integrity is vital, such as commercial banks, secret service organizations etc. Even though this algorithm is feasible to implement in software, it is impractical to achieve desired performance for most of the applications. Hence, a hardware solution is highly recommended. Prior art DES hardware in CMOS technology served performance needs of low-end and mid-range systems only, due to the technology constraints. However, some of these constraints are removed through the technology breakthroughs and the current CMOS is well suited for high performance applications. While prior art DES designs allowed one round per cycle to minimize the cell count, the current technology allows of multiple rounds per cycle due to the denser CMOS chip technology.