Patents by Inventor James Patrick Wood

James Patrick Wood has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6448169
    Abstract: An apparatus for use in manufacturing a semiconductor device includes an input-output (IO) face having a plurality of IO lands, and is situated in an operating position in abutting relation with a depositor. The apparatus includes a first holding member holding the depositor in a first position; a second holding member holding the semiconductor device in the operating position. The depositor and the semiconductor device cooperate in the operating position to deposit solder ball connection structures to the IO lands. The apparatus further includes a separating member for moving at least one of the depositor and the semiconductor device from the operating position to an interim orientation. The interim orientation establishes a separation distance intermediate the depositor and the semiconductor device appropriate to disengage the solder ball connecting structures from the depositor.
    Type: Grant
    Filed: December 21, 1995
    Date of Patent: September 10, 2002
    Assignee: International Business Machines Corporation
    Inventors: William Brearley, Laertis Economikos, Paul F. Findeis, Kimberley A. Kelly, Bouwe W. Leenstra, Arthur Gilman Merryman, Eric Daniel Perfecto, Chandrika Prasad, James Patrick Wood, Roy Yu
  • Patent number: 6149048
    Abstract: An apparatus for use in manufacturing a semiconductor device includes an input-output (IO) face having a plurality of IO lands, and is situated in an operating position in abutting relation with a depositor. The apparatus includes a first holding member holding the depositor in a first position; a second holding member holding the semiconductor device in the operating position. The depositor and the semiconductor device cooperate in the operating position to deposit solder ball connection structures to the IO lands. The apparatus further includes a separating member for moving at least one of the depositor and the semiconductor device from the operating position to an interim orientation. The interim orientation establishes a separation distance intermediate the depositor and the semiconductor device appropriate to disengage the solder ball connecting structures from the depositor.
    Type: Grant
    Filed: April 8, 1998
    Date of Patent: November 21, 2000
    Assignee: International Business Machines Corporation
    Inventors: William Brearley, Laertis Economikos, Paul F. Findeis, Kimberley A. Kelly, Bouwe W. Leenstra, Arthur Gilman Merryman, Eric Daniel Perfecto, Chandrika Prasad, James Patrick Wood, Roy Yu
  • Patent number: 6099935
    Abstract: An apparatus for use in manufacturing a semiconductor device having input-output (IO) lands arranged in an IO array on an IO face includes a body having a plurality of cavities extending from an operating face into the body; the cavities are arranged in a cavity loci array which is in registeration with the IO lands when the apparatus is in a manufacturing position with the operating face generally adjacent the IO face. Each cavity has a depth and a lateral expanse which cooperate to establish a volume defined by a cavity bottom and at least one cavity wall. The volume accommodates an appropriate amount of solder material to establish a measure of the solder material on a facing IO land when the apparatus is in the manufacturing position.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: August 8, 2000
    Assignee: International Business Machines Corporation
    Inventors: William Brearley, Laertis Economikos, Paul F. Findeis, Kimberley A. Kelly, Bouwe W. Leenstra, Arthur Gilman Merryman, Eric Daniel Perfecto, Chandrika Prasad, James Patrick Wood, Roy Yu
  • Patent number: 5735452
    Abstract: A method for forming a ball grid array to provide a chip carrier with I/O capabilities is described. The method includes combining three distinct steps into one: partitioning a solder sheet into identical solder pieces using a mask provided with openings that match the footprint of the chip carrier; reflowing the solder pieces into solder balls; and joining the balls to the I/O pads of the chip carrier. By combining these three steps into one, a high throughput, high volume, defect free and contamination free operation for forming I/O connections thus results.
    Type: Grant
    Filed: June 17, 1996
    Date of Patent: April 7, 1998
    Assignee: International Business Machines Corporation
    Inventors: Roy Yu, William Harrington Brearley, Kimberley Ann Kelly, Patrick Michael O'Leary, Arthur Gilman Merryman, James Patrick Wood
  • Patent number: 5722579
    Abstract: Multi-chip modules provided with a pin array may, under close scrutiny, display certain defects that may cause reliability problems. The presence of even one such defect necessitates the scrapping of the module. A method of salvaging the module is described, wherein the module is reworked by the method comprising the steps of applying a shearing force against the pins. During which the module is exposed to a temperature at or above that which is necessary for softening the braze material to remove the pins; polishing the surface of the module including the pads; evaporating the new pads; and attaching new pins to the pads.
    Type: Grant
    Filed: April 26, 1996
    Date of Patent: March 3, 1998
    Assignee: International Business Machines Corporation
    Inventors: Roy Yu, James Patrick Wood, Thomas Michael Biruk, Gregory Scott Boettcher, William Harrington Brearley, Kimberley Ann Kelly, Bouwe William Leenstra, Arthur Gilman Merryman