Abstract: A testing system can perform scalability testing on a target system, including automatically identifying a performance bottleneck component of the target system when the target system includes multiple components. The testing system can specify a target load of a specified component of the target system. The testing system can provide a simulated request to the target system and measure performance of the target system. Based on the measurement, the testing system can determine a scaling factor. The testing system can scale up the simulated request by the scaling factor, and determine whether one or more components of the target system have reached full capacity. The testing system can then adjust the scaling factor and the simulated request, until the testing system identifies a component of the target system that is a performance bottleneck of the target system when a specific number of requests are provided.

Abstract: A diversity receiver includes a first RF front end module for receiving a first RF signal, and frequency converting the first RF signal and outputting a first diversity signal, a second RF front end module for receiving a second RF signal, frequency converting the second RF signal and outputting a second diversity signal, a first converter for converting the first diversity signal to a first time-domain signal, a second converter for converting the second diversity signal to a second time-domain signal, a first transformer for translating the first time-domain signal to a first frequency-domain signal, a second transformer for translating the second time-domain signal to a second frequency-domain signal, a first pre-equalizer for equalizing the first frequency-domain signal, a second pre-equalizer for equalizing the second frequency-domain signal, and a combiner for combining the first and second pre-equalized frequency-domain signals.

Abstract: A communication receiver which applies signal processing for quantitatively estimating receive signal factors such as communication channel quality, signal characteristics, and overall system received bit error rate (BER) or packet error rate (PER) and which applies a general algorithm for mapping these estimated factors to control receiver performance and minimize power consumption.

Abstract: A circuit for self-calibrating a gain control system samples the output of a digital amplifier coupled in series with one or more analog amplifiers to correct errors in a discrete stepped gain control. A digital gain control circuit controls both the digital amplifier and at least one analog amplifier to produce a smooth linear and continuous gain, wherein perturbations in the digital control of gain are smoothed by a signal applied to gain control circuit by a gain step correction circuit.

Abstract: A circuit for self-calibrating a gain control system samples the output of a digital amplifier coupled in series with one or more analog amplifiers to correct errors in a discrete stepped gain control. A digital gain control circuit controls both the digital amplifier and at least one analog amplifier to produce a smooth linear and continuous gain, wherein perturbations in the digital control of gain are smoothed by a signal applied to gain control circuit by a gain step correction circuit.

Abstract: A circuit for self-calibrating a gain control system samples the output of a digital amplifier coupled in series with one or more analog amplifiers to correct errors in a discrete stepped gain control. A digital gain control circuit controls both the digital amplifier and at least one analog amplifier to produce a smooth linear and continuous gain, wherein perturbations in the digital control of gain are smoothed by a signal applied to gain control circuit by a gain step correction circuit.

Abstract: A circuit for self-calibrating a gain control system samples the output of a digital amplifier coupled in series with one or more analog amplifiers to correct errors in a discrete stepped gain control. A digital gain control circuit controls both the digital amplifier and at least one analog amplifier to produce a smooth linear and continuous gain, wherein perturbations in the digital control of gain are smoothed by a signal applied to gain control circuit by a gain step correction circuit.

Abstract: A diversity receiver includes a first RF front end module for receiving a first RF signal, and frequency converting the first RF signal and outputting a first diversity signal, a second RF front end module for receiving a second RF signal, frequency converting the second RF signal and outputting a second diversity signal, a first converter for converting the first diversity signal to a first time-domain signal, a second converter for converting the second diversity signal to a second time-domain signal, a first transformer for translating the first time-domain signal to a first frequency-domain signal, a second transformer for translating the second time-domain signal to a second frequency-domain signal, a first pre-equalizer for equalizing the first frequency-domain signal, a second pre-equalizer for equalizing the second frequency-domain signal, and a combiner for combining the first and second pre-equalized frequency-domain signals.

Abstract: A communication receiver which applies signal processing for quantitatively estimating receive signal factors such as communication channel quality, signal characteristics, and overall system received bit error rate (BER) or packet error rate (PER) and which applies a general algorithm for mapping these estimated factors to control receiver performance and minimize power consumption.

Abstract: A circuit for self-calibrating a gain control system samples the output of a digital amplifier coupled in series with one or more analog amplifiers to correct errors in a discrete stepped gain control. A digital gain control circuit controls both the digital amplifier and at least one analog amplifier to produce a smooth linear and continuous gain, wherein perturbations in the digital control of gain are smoothed by a signal applied to gain control circuit by a gain step correction circuit.