Abstract: An oscillator has timing characteristics that are determined by resistor and capacitor values. The circuit comprises an astable multivibrator and a current reference. The multivibrator comprises a first and a second timing capacitor. The multivibrator is configured to produce an oscillating output signal in response to charging and discharging the first and the second timing capacitors. The current reference is configured to control the rate of change of charge of the first and second timing capacitors. The current reference is determined in part by the resistor values.

Abstract: The crowbar current in a driver inverter, which has a pair of complementary driver transistors, is substantially reduced by adjusting the turn on and turn off times of the p-channel and n-channel driver transistors such that each driver transistor turns on after the other driver transistor has been turned off.

Abstract: An apparatus for an improved output buffer includes a symmetrical pre-gain stage and a gain stage. The pre-gain stage includes a pair of matched differential amplifiers that are arranged to provide a differential intermediary signal. The gain stage is arranged to receive the differential intermediary signal and provide a single-ended output signal. The pre-gain stage differential amplifiers include transistors that are arranged as differential pairs, where each of differential pair transistors is minimally sized to provide very low capacitive loading. The pre-gain stage differential amplifiers are matched such that symmetrical amplification is obtained from the differential intermediary signal. The pre-gain stage arrangement provides for a differential intermediary signal such that common-mode noise rejection and power supply noise rejection are enhanced.

Abstract: A power-off protection circuit for an LVDS line-driver eliminates initialization problems in a local LVDS driver circuit that are caused by a remote LVDS river when the local LVDS driver is disabled. The remote LVDS driver may introduce a signal into the substrate of the local LVDS driver when the local LVDS driver is in a power-off mode. A current source in the local LVDS driver couples power from a local power supply node to the local LVDS driver when power is active. A method and protection circuit connects the substrate of the current source to the local power supply when power is active, and decouples the substrate from the local power supply when power is deactivated. The remote LVDS driver cannot cause a false power supply signal in the local LVDS driver since the conduction path is disconnected. A first switching element couples a floating substrate node in the current source to the local power supply when the power is active.

Abstract: A power-off protection circuit for an LVDS line-driver eliminates initialization problems in a local LVDS driver circuit that are caused by a remote LVDS driver when the local LVDS driver is disabled. The remote LVDS driver may introduce a signal into the substrate of the local LVDS driver when the local LVDS driver is in a power-off mode. A current source in the local LVDS driver couples power from a local power supply node to the local LVDS driver when power is active. A method and protection circuit connects the substrate of the current source to the local power supply when power is active, and decouples the substrate from the local power supply when power is deactivated. The remote LVDS driver cannot cause a false power supply signal in the local LVDS driver since the conduction path is disconnected. A first switching element couples a floating substrate node in the current source to the local power supply when the power is active.

Abstract: A differential output driver circuit produces a differential output signal in response to an input data signal. The differential output driver circuit provides for a controlled edge rate in the differential output signal when the input data signal changes logic states. Control signals are generated using an adjustable delay circuit, each subsequent control signal being delayed in time from the preceding control signal by a unit delay time. The control signals control N output drivers, each of the N output drivers having an output signal coupled to the differential output signal, and each contributing a portion of the differential output signal. When the input data signal changes from one logic state to another, the differential output signal will have a defined edge rate determined by the unit delay time and the contributing portion from each of the N output drivers. In one example, the unit delay time is determined by a delay time through a buffer that has a controlled current limit.

Abstract: A power supply regulator circuit with increased rejection of variations and noise in power supply voltage which is particularly well suited to isolating a voltage-controlled oscillator (VCO) from such power supply variations and noise. The regulator circuit uses an operational amplifier connected as a voltage follower circuit to buffer the reference voltage provided as the regulated supply potential for the VCO. This buffered voltage is also used to establish the bias voltage across a current mirror circuit which is powered by the unregulated power supply and through which the supply current for the VCO flows. This circuit topography requires no compensation capacitance and, therefore, provides increased rejection of variations and noise in the power supply voltage.

Abstract: A receiver includes first and second input nodes and a differential receiver having first and second inputs respectively connected to the first and second input nodes, as well as first and second outputs. First and second delay circuits are respectively connected to the first and second outputs of the differential receiver. First and second single-ended receivers each having an input are respectively connected to the first and second input nodes, the first and second single-ended receivers each having an output. Input glitch prevention circuitry includes third and fourth delay circuits that are respectively connected to the outputs of the first and second single-ended receivers and an OR gate having separate inputs that are respectively connected to the outputs of the first and second single-ended receivers and the outputs of the third and fourth delay circuits.

Abstract: A driver which includes an output node and an output transistor connected between the output node and a first voltage reference node. A CMOS inverter is connected to a gate of the output transistor and includes a first p-channel transistor and a first n-channel transistor that have their gates connected together. A capacitance transistor is connected to the output node and the CMOS inverter and is configured to create a capacitance therebetween. A shifting transistor has its drain-source conducting path connected in series with a drain of the first p-channel transistor and a drain of the first n-channel transistor and is configured to maintain the capacitance transistor in accumulation mode.

Abstract: A driver for providing binary signals from a data system to a transmission line includes a data input node and an output transistor coupled between a data output node and ground. The output transistor has a gate, a source and a corresponding gate-source voltage therebetween. A first transistor is coupled to the gate of the output transistor and is responsive to signals applied to the input node. It conducts a discharge current from the gate of the output transistor for discharging the gate of the output transistor to reduce its gate-source voltage. A clamping circuit clamps the gate-source voltage of the output transistor to a first voltage level above ground to prevent the discharge current from reducing the, gate-source voltage of the output transistor to ground.

Abstract: A high speed differential data latch includes identical master and slave flip-flops. The master flip-flop is driven by a differential input data signal while both flip-flops are driven by a shared differential clock signal. Each flip-flop includes: one differential amplifier for sequentially latching the differential input data signal to provide a differential output data signal; a second differential amplifier for generating two switched supply currents from the clock signal for powering the differential data amplifier; and a third differential amplifier cross-coupled to the differential data amplifier for providing positive feedback thereto for enhancing the latching speed. The differential output data signal follows the differential input data signal during one of the differential clock states and remains latched during the other differential clock state.

Abstract: A high-speed transmission line receiver includes a basic differential amplifier stage along with a gain enhancement stage, which is generally similar to the differential amplifier stage. One of the current mirror transistors in the gain enhancement stage is connected to one of the current mirror transistors in the basic amplifier stage in such a way that the magnitude of the differential current at the output of the basic amplifier stage is increased, thereby increasing the gain of the receiver without increasing its output capacitance or the time constant of the output signal. Preferably, the transistors in the gain enhancement stage are larger than the transistors in the basic amplifier stage. Increasing the gain of the line receiver reduces the distortion which may occur as a result of the failure of the line receiver to reach a clamping voltage as the common mode of the differential input signal is increased.

Abstract: A charge pump of a phase-locked loop includes a first P channel transistor and a first N channel transistor coupled to mirror a current in a constant current source. The P channel transistor and N channel transistor are formed with dimensions that match transient responses of currents through the N and P channel transistors during switching rather than matching the gains of the N and P channel transistors. In one embodiment, the channel length of the N channel transistor is twice a channel length of the P channel transistor. A second P channel transistor and a second N channel transistor connected in series with the first P and N channel transistors switch the current through the first P channel transistor and the first N channel transistor respectively. The second P channel transistor and the second N channel transistor have matched gate-drain capacitances so that they have the same switching speed.

Abstract: A driver for providing binary signals from a data system to a transmission line is disclosed. A first n-channel transistor has its drain coupled to the transmission line and its source coupled to ground. The channel of the first n-channel transistor has a width that is greater than its length. A first inverter stage conducts current from a first voltage supply to the gate of the first n-channel transistor in order to switch the first n-channel transistor into a conductive state and conducts current from the gate of the first n-channel transistor to ground in order to switch the first n-channel transistor into a non-conductive state. A discharge circuit provides a discharge path from the gate of the first n-channel transistor to ground during a discharge time period and then removes the discharge path at the end of the discharge time period.

Abstract: A temperature compensation circuit is disclosed that includes a first field-effect transistor (FET), a second FET, a resistor, and current generating circuitry. The second FET has a larger current conducting channel than the current conducting channel of the first FET, and the gate of the second FET is coupled to the gate of the first FET. The resistor is coupled between a first node that is common with the source of the first FET and a second node that is common with the source of the second FET. The current generating circuitry generates and maintains substantially equal drain currents in the first and second FETs.

Abstract: A driver for providing binary signals from a data system to a transmission line and a method of charging and discharging the driver output transistor is disclosed. A preferred embodiment of the driver includes an output transistor having its drain-source circuit connectable between the transmission line and ground. An input stage provides a first charging current to the gate of the output transistor for a first charging time period and a first discharging current for discharging the gate of the output transistor for a first discharging time period. A first falling edge speed-up circuit provides a second charging current to the gate of the output transistor for a second charging time period to charge the voltage level of the gate of the output transistor to approximately its threshold voltage level.

Abstract: A storage charge reduction circuit for reducing the storage charge of a first bipolar transistor. The circuit includes a second field effect transistor connectable between the base of the first bipolar transistor and ground for conducting a compensation current from the base of the first bipolar transistor to ground. A third bipolar transistor is connected in series with a first resistor for conducting a first current from a first voltage supply through the first resistor to ground. Current mirror circuitry sets the gate-source voltage of the second field effect transistor so that the compensation current is proportional to the first current. The first current and the compensation current increase when temperature increases. In a preferred embodiment, the storage charge reduction circuit is used in a transmission line driver. The driver includes an output bipolar transistor connectable between the transmission line and ground for conducting current from the transmission line to ground.

Abstract: A data transceiver includes a transmitter connected at one end of a data transmission line and a receiver connected at the other end of the data transmission line. At least some portions of the transceiver are formed in CMOS. A temperature compensation circuit is connected to selected components of the transceiver to correct for temperature-induced variations in currents through those components. The temperature compensation circuit includes a pair of transistors connected, respectively, in parallel conduction paths. The transistors have unequal emitter areas, and their gates are tied together. The current through the larger transistor varies directly with temperature, and this current is reflected in a current mirror transistor that is connected to the shorted gates of the transistor pair. Since in CMOS technology current varies inversely with temperature, the current through the mirror transistor provides temperature compensation for selected components of the transceiver.

Abstract: A translator circuit amplifies a pair of differential input signals to produce a pair of intermediate differential signals by utilizing a pair of cross-coupled differential gain stages. The gain stages amplify the input signals to balance the capacitive loading. The pair of intermediate differential signals are formed to be substantially equal and 180.degree. out of phase. The current sources of the gain stages are connected together and controlled by the outputs of the gain stages to reduce the rise and fall times of the intermediate differential signals. The translator circuit also converts the pair of intermediate differential signals to a single-ended output signal by utilizing a first differential pair to produce the output signal, and a second differential pair to adaptively control the current source of the first differential pair, thereby reducing the rise and fall times of the output signal. As a result, the translator circuit is capable of producing the output signal with minimum distortion.

Abstract: A receiver for providing binary signals from a transmission line to a data system is disclosed. The receiver includes a differential comparator for comparing a reference voltage to an input voltage and for providing a comparator output signal in response to the comparison. The comparator output signal indicates whether the input voltage is greater or less than the reference voltage. A first current source is coupled to the differential comparator for providing current to the differential comparator. The first current source provides substantially the same amount of current to the differential comparator whether the input voltage is greater or less than the reference voltage, and the first current source has a positive temperature coefficient so that when temperature increases the current provided by the first current source increases. A middle stage amplifies the comparator output signal to produce a middle stage output signal and compensates the middle stage output signal for variations in temperature.