Abstract: Generally discussed herein are systems, devices, and methods for data interpolation. A system for data interpolation can include first circuitry to split a set of data into four disjoint subsets including first, second, third, and fourth subsets and load each of the disjoints subsets into respective first, second, third, and fourth memory portions, second circuitry to retrieve, simultaneously, data from each of the first, second, third, and fourth memory portions, and interpolation circuitry to perform, based on the retrieved data, data interpolation.

Abstract: A predictive semi-active laser (SAL) pulse correlator includes a history buffer, a correlation predictor, a match identifier and a correlation verifier. The history buffer is configured to store an indicator for each of a plurality of received pulses. The correlation predictor is configured to initiate a search of the history buffer for a pulse train match for a future interval and to predict correlation for the future interval when the pulse train match is found. The match identifier is configured to search the history buffer for a specified number of pulse matches corresponding to the pulse train match. The correlation verifier is configured to verify correlation by receiving a pulse during the future interval when the correlation predictor predicts correlation for the future interval.

Abstract: Generally discussed herein are systems, devices, and methods for data interpolation. A system for data interpolation can include first circuitry to split a set of data into four disjoint subsets including first, second, third, and fourth subsets and load each of the disjoints subsets into respective first, second, third, and fourth memory portions, second circuitry to retrieve, simultaneously, data from each of the first, second, third, and fourth memory portions, and interpolation circuitry to perform, based on the retrieved data, data interpolation.

Abstract: A predictive semi-active laser (SAL) pulse correlator includes a history buffer, a correlation predictor, a match identifier and a correlation verifier. The history buffer is configured to store an indicator for each of a plurality of received pulses. The correlation predictor is configured to initiate a search of the history buffer for a pulse train match for a future interval and to predict correlation for the future interval when the pulse train match is found. The match identifier is configured to search the history buffer for a specified number of pulse matches corresponding to the pulse train match. The correlation verifier is configured to verify correlation by receiving a pulse during the future interval when the correlation predictor predicts correlation for the future interval.

Abstract: An apparatus includes multiple oscillators, where each oscillator includes an inverter chain. The apparatus also includes combinatorial logic configured to generate a random number having one or more bits. The combinatorial logic is configured to generate each bit by combining two or more signals from at least two oscillators that have inverter chains with different prime numbers of inverters. The combinatorial logic may be configured to generate each bit using signals from a unique combination of oscillators. The combinatorial logic may also be configured to combine the signals asynchronously and sample the combined signal synchronously using a synchronous sampling clock, where at least one of the signals is not harmonically related to the sampling clock. Each of at least one of the oscillators may include multiple taps configured to provide multiple signals, and the multiple signals from one oscillator could have different asynchronous phases relative to the sampling clock.

Abstract: An apparatus includes multiple oscillators, where each oscillator includes an inverter chain. The apparatus also includes combinatorial logic configured to generate a random number having one or more bits. The combinatorial logic is configured to generate each bit by combining two or more signals from at least two oscillators that have inverter chains with different prime numbers of inverters. The combinatorial logic may be configured to generate each bit using signals from a unique combination of oscillators. The combinatorial logic may also be configured to combine the signals asynchronously and sample the combined signal synchronously using a synchronous sampling clock, where at least one of the signals is not harmonically related to the sampling clock. Each of at least one of the oscillators may include multiple taps configured to provide multiple signals, and the multiple signals from one oscillator could have different asynchronous phases relative to the sampling clock.