Abstract: A processor coupled to memory is configured to receive image data based on an image captured by a camera of a vehicle. The image data is used as a basis of an input to a trained machine learning model trained to predict a three-dimensional trajectory of a machine learning feature. The three-dimensional trajectory of the machine learning feature is provided for automatically controlling the vehicle.

Abstract: A processor coupled to memory is configured to receive image data based on an image captured by a camera of a vehicle. The image data is used as a basis of an input to a trained machine learning model trained to predict a three-dimensional trajectory of a machine learning feature. The three-dimensional trajectory of the machine learning feature is provided for automatically controlling the vehicle.

Abstract: Systems, apparatuses, and methods for instruction next fetch prediction. A scan-on-fill target predictor in a processor generates a predicted next fetch address for the instruction fetch unit. When a group of instructions is used to fill an instruction cache but is not currently being retrieved from the instruction cache for processing by other pipeline stages, the group of instructions are scanned to identify exit points of basic blocks within the group. An entry of a table in the scan-on-fill target predictor is allocated for an instruction in a basic block in the group when the basic block has an exit point with a target address that can be resolved within a single clock cycle. The scan-on-fill target predictor may perform a lookup of the table with the current fetch address. The prediction may be compared to a main branch predictor at a later pipeline stage for training purposes.

Abstract: A processor coupled to memory is configured to receive image data based on an image captured by a camera of a vehicle. The image data is used as a basis of an input to a trained machine learning model trained to predict a three-dimensional trajectory of a machine learning feature. The three-dimensional trajectory of the machine learning feature is provided for automatically controlling the vehicle.

Abstract: A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating “makefiles” for purposes of simulation and/or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed.

Abstract: A microprocessor architecture having extendible logic. One or more customized applications are available to the instruction pipeline. The customizable applications may include software, extension logic instruction or register, dynamically configurable hardware logic, or combinations of these. In order to enable the operating system to interface with the customized extension applications, at least one software extension is provided to the operating system. When a specific extension is requested a software exception is generated by the OS. In response to the exception, the least one software extension is called to handle context switch and dynamic configuration of the extendible logic of the microprocessor.

Abstract: A microprocessor architecture having extendible logic. One or more customized applications are available to the instruction pipeline. The customizable applications may include software, extension logic instruction or register, dynamically configurable hardware logic, or combinations of these. In order to enable the operating system to interface with the customized extension applications, at least one software extension is provided to the operating system. When a specific extension is requested a software exception is generated by the OS. In response to the exception, the least one software extension is called to handle context switch and dynamic configuration of the extendible logic of the microprocessor.

Abstract: A processor includes guest mode control registers supporting guest mode operating behavior defined by guest context specified in the guest mode control registers. Root mode control registers support root mode operating behavior defined by root context specified in the root mode control registers. The guest context and the root context are simultaneously active to support virtualization of hardware resources such that multiple operating systems supporting multiple applications are executed by the hardware resources.

Abstract: A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating “makefiles” for purposes of simulation and/or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed.

Abstract: A processor includes a first translation look-aside buffer to support a guest operating mode. A second translation look-aside buffer supports a root operating mode. Hardware resources support the guest operating mode as controlled by guest mode control registers defining guest context. The guest context is used by the hardware resources to access the first translation look-aside buffer to translate a guest virtual address to a guest physical address. The hardware resources access the second translation look-aside buffer to translate the guest physical address to a physical address.

Abstract: A processor includes a first translation look-aside buffer to support a guest operating mode. A second translation look-aside buffer supports a root operating mode. Hardware resources support the guest operating mode as controlled by guest mode control registers defining guest context. The guest context is used by the hardware resources to access the first translation look-aside buffer to translate a guest virtual address to a guest physical address. The hardware resources access the second translation look-aside buffer to translate the guest physical address to a physical address.

Abstract: A processor includes guest mode control registers supporting guest mode operating behavior defined by guest context specified in the guest mode control registers. Root mode control registers support root mode operating behavior defined by root context specified in the root mode control registers. The guest context and the root context are simultaneously active to support virtualization of hardware resources such that multiple operating systems supporting multiple applications are executed by the hardware resources.

Abstract: A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating “makefiles” for purposes of simulation and/or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed.

Abstract: An improved method and apparatus for controlling and implementing instructions in a pipelined central processing unit (CPU) or user-customizable microprocessor. In a first aspect of the invention, an improved method of permitting programmer control of jump instruction interlocks is disclosed. In one embodiment, a minimum of one cycle is required between an instruction that sets flags and a branch taken as a result of those flags; an interlock is used to detect a branch preceded by an instruction setting the flags to ensure that the instruction immediately preceding the branch can not affect the branch outcome. In a second embodiment, a jump instruction following a flag setting instruction whose flags may affect the outcome of the jump is stalled until all flags are set. In a second aspect of the invention, a method of synthesizing a processor design incorporating the aforementioned interlocks is disclosed.

Abstract: A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating “makefiles” for purposes of simulation and/or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed.

Abstract: An improved method and apparatus for controlling and implementing instructions in a pipelined central processing unit (CPU) or user-customizable microprocessor. In a first aspect of the invention, an improved method of permitting programmer control of jump instruction interlocks is disclosed. In one embodiment, a minimum of one cycle is required between an instruction that sets flags and a branch taken as a result of those flags; an interlock is used to detect a branch preceded by an instruction setting the flags to ensure that the instruction immediately preceding the branch can not affect the branch outcome. In a second embodiment, a jump instruction following a flag setting instruction whose flags may affect the outcome of the jump is stalled until all flags are set. In a second aspect of the invention, a method of synthesizing a processor design incorporating the aforementioned interlocks is disclosed.

Abstract: An improved method and apparatus for controlling and implementing instructions in a pipelined central processing unit (CPU) or user-customizable microprocessor. In a first aspect of the invention, an improved method of permitting programmer control of jump instruction interlocks is disclosed. In one embodiment, a minimum of one cycle is required between an instruction that sets flags and a branch taken as a result of those flags; an interlock is used to detect a branch preceded by an instruction setting the flags to ensure that the instruction immediately preceding the branch can not affect the branch outcome. In a second embodiment, a jump instruction following a flag setting instruction whose flags may affect the outcome of the jump is stalled until all flags are set. In a second aspect of the invention, a method of synthesizing a processor design incorporating the aforementioned interlocks is disclosed.