Abstract: A processor in accordance with the present invention includes memory that stores test data and control data. The processor also includes a test application that transmits the test data and the control data from the processor's memory to a test access port of the processor. The test access port then utilizes the test data and the control data to capture state data that defines at least one state of the processor while the processor is executing. This test data may be analyzed via conventional techniques to detect and isolate errors in the execution of the processor.

Abstract: The queue management control system according to the present invention provides a system that elegantly handles unlimited queue deletions without bubbles. The queue management control system is comprised of: a plurality of item registers; and a control logic block electrically coupled to the plurality of item registers. The control logic block includes an item tracking means, a plurality of pointer registers, and an item ordering means. The pointer registers are connected in a loop configuration so that the order of the contents of the pointer registers mirrors the behavior of a FIFO queue. Because of the one-to-one correspondence between the values stored in the pointer storage registers and the item registers, the contents of each pointer register may be mapped to a particular item register. This allows tracking of the order of the items in the item register to be serviced by the servicing logic by the contents of the pointer register.

Abstract: A computing system includes a processor, a main memory, a first level cache and a second level cache. The second level cache contains data lines. The first level cache contains data line fragments of data lines within the second level cache. In response to a processor attempt to access a data word, a cache controller searches for the data word in the first level cache. When a first level cache miss results from the attempted access, a search is made for the data word in the second level cache. When a second level cache miss results a new data line, which contains the data word, is fetched from the main memory. Concurrently, the cache controller determines which entries of the first level cache are invalid. Once the new data line is fetched from the main memory, the new data line is placed in the second level cache, replacing the second level victim cache line. In addition, as many data line fragments as possible from the new data line are placed into invalid entries in the first level cache.

Abstract: The individual RAMs comprising the memory space of a computer are automatically located within a memory space during initialization and address enable information is stored in ID-RAMs on each RAM card. Shift registers on the RAM cards are connected in series and during initialization an ID bit is serially clocked through the shift registers. At each clock pulse the contents of the shift registers are written to the ID-RAMs of each RAM card. The presence of an ID bit at a specific memory location in an ID-RAM on a RAM card indicates that that card is to be enabled when the memory location address is accessed; the location of the ID bit within the memory location indicates the particular RAM on the RAM card to be accessed.

Abstract: The individual RAMs comprising the memory space of a computer may be of various sizes and are automatically located within a memory space during initialization and address enable information is stored in ID-RAMs on each RAM card. Shift registers on the RAM cards are connected in series and an ID bit is serially clocked through the shift registers during initialization. At each clock pulse the contents of the shift registers are written to the ID-RAMs of each RAM card. The presence of an ID bit at a specific memory location in an ID-RAM on a RAM card indicates that card is to be enabled when the memory location address is accessed; the location of the ID bit within the memory location indicates the particular RAM on the RAM card to be accessed. A detector monitors a transfer of the ID bit between adjacent shift registers so that card memory boundaries, and RAM size, may be known.