Patents by Inventor James S. Ignowski
James S. Ignowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10490270Abstract: A circuit includes a resistive memory cell in a memory array to store a memory state for the resistive memory cell. A reference cell in the memory array stores a reference memory state for the resistive memory cell. A function generator concurrently applies a read voltage to the resistive memory cell and the reference cell via a memory row address. A sensing circuit enables the function generator and monitors a target current received from the resistive memory cell when selected via a memory column address and monitors a reference current received when selected via a reference column address in response to the read voltage applied to the memory row address. A current comparator circuit in the sensing circuit compares a difference between the target current and the reference current to determine the memory state of the resistive memory cell.Type: GrantFiled: October 28, 2015Date of Patent: November 26, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: James S Ignowski, Martin Foltin, Yoocharn Jeon
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Patent number: 10331186Abstract: In an embodiment, a processor comprises: a plurality of cores each to execute instructions; a plurality of thermal sensors, at least one of which is associated with each of the cores; and a power control unit (PCU) coupled to the cores. The PCU includes a thermal control logic to preemptively throttle a first core by a first throttle amount when a temperature of a second core exceeds at least one thermal threshold. Note that this first core may be preemptively throttled independently of a throttling of the second core and may have a temperature of the first core does not exceed any thermal threshold. Other embodiments are described and claimed.Type: GrantFiled: January 9, 2017Date of Patent: June 25, 2019Assignee: Intel CorporationInventors: James S. Ignowski, Matthew M. Bace, Eric J. Dehaemer, Chris Poirier
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Publication number: 20180301187Abstract: A circuit includes a resistive memory cell in a memory array to store a memory state for the resistive memory cell. A reference cell in the memory array stores a reference memory state for the resistive memory cell. A function generator concurrently applies a read voltage to the resistive memory cell and the reference cell via a memory row address. A sensing circuit enables the function generator and monitors a target current received from the resistive memory cell when selected via a memory column address and monitors a reference current received when selected via a reference column address in response to the read voltage applied to the memory row address. A current comparator circuit in the sensing circuit compares a difference between the target current and the reference current to determine the memory state of the resistive memory cell.Type: ApplicationFiled: October 28, 2015Publication date: October 18, 2018Inventors: James S IGNOWSKI, Martin FOLTIN, Yoocharn JEON
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Patent number: 9972387Abstract: This disclosure provides a circuit that includes a ramp generator to apply a voltage ramp to a resistive memory cell. A sensing circuit can enable the ramp generator and monitor a current output received from the resistive memory cell in response to the applied voltage ramp, wherein the sensing circuit compares the current output to a predetermined current threshold to determine the state of the resistive memory cell.Type: GrantFiled: October 31, 2014Date of Patent: May 15, 2018Assignee: Hewlett Packard Enterprise Development LPInventors: Martin Foltin, Yoocharn Jeon, Brent Buchanan, Erik Ordentlich, Naveen Muralimanohar, James S. Ignowski, Jacquelyn M. Ingemi
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Patent number: 9934854Abstract: A memory controller includes a voltage driver and a voltage comparator. The voltage driver applies a variable voltage to a selected line of a crossbar array to determine a first measured voltage that drives a first read current through a selected memory cell of the crossbar array. The voltage driver applies the variable voltage to the selected line to determine a second measured voltage that drives a second read current through the selected memory cell. The voltage comparator then determines a voltage difference between the first measured voltage and the second measured voltage and to compare the voltage difference with a reference voltage difference to determine a state of the selected memory cell. The crossbar array comprises a plurality of row lines, a plurality of column lines, and a plurality of memory cells. Each memory cell is coupled between a unique combination of one row line and one column line.Type: GrantFiled: November 14, 2014Date of Patent: April 3, 2018Assignee: Hewlett Packard Enterprise Development LPInventors: Yoocharn Jeon, James S. Ignowski
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Publication number: 20170249987Abstract: A memory controller includes a voltage driver and a voltage comparator. The voltage driver applies a variable voltage to a selected line of a crossbar array to determine a first measured voltage that drives a first read current through a selected memory cell of the crossbar array. The voltage driver applies the variable voltage to the selected line to determine a second measured voltage that drives a second read current through the selected memory cell. The voltage comparator then determines a voltage difference between the first measured voltage and the second measured voltage and to compare the voltage difference with a reference voltage difference to determine a state of the selected memory cell. The crossbar array comprises a plurality of row lines, a plurality of column lines, and a plurality of memory cells. Each memory cell is coupled between a unique combination of one row line and one column line.Type: ApplicationFiled: November 14, 2014Publication date: August 31, 2017Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: Yoocharn JEON, James S. IGNOWSKI
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Publication number: 20170206956Abstract: This disclosure provides a circuit that includes a ramp generator to apply a voltage ramp to a resistive memory cell. A sensing circuit can enable the ramp generator and monitor a current output received from the resistive memory cell in response to the applied voltage ramp, wherein the sensing circuit compares the current output to a predetermined current threshold to determine the state of the resistive memory cell.Type: ApplicationFiled: October 31, 2014Publication date: July 20, 2017Inventors: Martin Foltin, Yoocharn Jeon, Brent Buchanan, Erik Ordentlich, Naveen Muralimanohar, James S. Ignowski, Jacquelyn M. Ingemi
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Publication number: 20170123467Abstract: In an embodiment, a processor comprises: a plurality of cores each to execute instructions; a plurality of thermal sensors, at least one of which is associated with each of the cores; and a power control unit (PCU) coupled to the cores. The PCU includes a thermal control logic to preemptively throttle a first core by a first throttle amount when a temperature of a second core exceeds at least one thermal threshold. Note that this first core may be preemptively throttled independently of a throttling of the second core and may have a temperature of the first core does not exceed any thermal threshold. Other embodiments are described and claimed.Type: ApplicationFiled: January 9, 2017Publication date: May 4, 2017Inventors: James S. Ignowski, Matthew M. Bace, Eric J. Dehaemer, Chris Poirier
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Patent number: 9575537Abstract: In an embodiment, a processor comprises: a plurality of cores each to execute instructions; a plurality of thermal sensors, at least one of which is associated with each of the cores; and a power control unit (PCU) coupled to the cores. The PCU includes a thermal control logic to preemptively throttle a first core by a first throttle amount when a temperature of a second core exceeds at least one thermal threshold. Note that this first core may be preemptively throttled independently of a throttling of the second core and may have a temperature of the first core does not exceed any thermal threshold. Other embodiments are described and claimed.Type: GrantFiled: July 25, 2014Date of Patent: February 21, 2017Assignee: Intel CorporationInventors: James S. Ignowski, Matthew M. Bace, Eric J. Dehaemer, Chris Poirier
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Publication number: 20160026231Abstract: In an embodiment, a processor comprises: a plurality of cores each to execute instructions; a plurality of thermal sensors, at least one of which is associated with each of the cores; and a power control unit (PCU) coupled to the cores. The PCU includes a thermal control logic to preemptively throttle a first core by a first throttle amount when a temperature of a second core exceeds at least one thermal threshold. Note that this first core may be preemptively throttled independently of a throttling of the second core and may have a temperature of the first core does not exceed any thermal threshold. Other embodiments are described and claimed.Type: ApplicationFiled: July 25, 2014Publication date: January 28, 2016Inventors: James S. Ignowski, Matthew M. Bace, Eric J. Dehaemer, Chris Poirier
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Patent number: 8368385Abstract: Methods and systems to detect droop events on-chip, which may include a sensor circuit located adjacent to a voltage node to convert a corresponding voltage to a digital count or value indicative of the voltage. The sensor circuit may include an n-stage ring oscillator and an asynchronous counter. The sensor circuit may include circuitry to capture and convert a phase associated with a count to a binary fractional value to increase voltage resolution. Multiple counts associated with the node may be evaluated at the node to identify minimum and maximum counts and corresponding time stamps. More complex evaluation and control circuitry may be shared amongst a plurality of sensor circuits and may include circuitry to generate and compare counts to one or more variable thresholds, circuitry to average counts over time, and memory to store state values associated with the sensors.Type: GrantFiled: September 25, 2009Date of Patent: February 5, 2013Assignee: Intel CorporationInventors: Aaron M. Barton, James S. Ignowski, Pablo Lopez, Mondira Pant, Rex Petersen, Robert Rose, Sean Welch
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Publication number: 20110074398Abstract: Methods and systems to detect droop events on-chip, which may include a sensor circuit located adjacent to a voltage node to convert a corresponding voltage to a digital count or value indicative of the voltage. The sensor circuit may include an n-stage ring oscillator and an asynchronous counter. The sensor circuit may include circuitry to capture and convert a phase associated with a count to a binary fractional value to increase voltage resolution. Multiple counts associated with the node may be evaluated at the node to identify minimum and maximum counts and corresponding time stamps. More complex evaluation and control circuitry may be shared amongst a plurality of sensor circuits and may include circuitry to generate and compare counts to one or more variable thresholds, circuitry to average counts over time, and memory to store state values associated with the sensors.Type: ApplicationFiled: September 25, 2009Publication date: March 31, 2011Inventors: Aaron M. Barton, James S. Ignowski, Pablo Lopez, Mondira Pant, Rex Petersen, Robert Rose, Sean Welch
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Publication number: 20080234953Abstract: Disclosed herein are different embodiments for estimating and/or controlling power consumption in a chip based on hot and cool temperatures in the chip.Type: ApplicationFiled: March 22, 2007Publication date: September 25, 2008Inventors: James S. Ignowski, Chris Bostak, Warren H. Parks
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Patent number: 7091796Abstract: A method for calibrating a voltage controlled oscillator (VCO) comprising applying a plurality of known voltages to the input of a VCO, monitoring, for each of the voltages, an output count from the VCO over a set interval, and storing the output counts for each voltage. Also disclosed is a system for calibrating a voltage controlled oscillator (VCO) comprising a plurality of known voltages, wherein the known voltage are connectable to the VCO, and a controller coupled to the output of the VCO, wherein the controller maintains a calibration table of VCO output counts for selected voltage inputs.Type: GrantFiled: August 20, 2003Date of Patent: August 15, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Christopher J. Bostak, Samuel D. Naffziger, Christopher A. Poirier, James S. Ignowski
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Patent number: 5734680Abstract: An analog, fully integrated, partial response maximum likelihood (PRML) read channel utilizing a high-performance analog delay line, an analog adaptive equalizer and an analog Viterbi detector is provided, resulting in saved space, performance gains, and lower power consumption. For signal detection and reconstruction used in read operations, the partial response maximum likelihood (PRML) read channel includes a variable gain amplifier coupled to a lowpass filter for input to an adaptive analog equalizer. The adaptive analog equalizer comprises an analog delay line and an analog feedforward equalizer (FFE). An analog Viterbi detector employs maximum-likelihood sequence estimation (MLSE) techniques to performs the signal detection function. A decoder/descrambler produces a final reconstructed signal. The analog implementation of a partial response maximum likelihood (PRML) read channel also includes a scrambler/encoder coupled to a write precompensation circuit for output to a separate write head.Type: GrantFiled: August 9, 1995Date of Patent: March 31, 1998Assignee: Hewlett-Packard Co.Inventors: Charles E. Moore, Richard A. Baumgartner, Travis N. Blalock, Thomas M. Walley, Robert A. Zimmer, Rajeev Badyal, Li Ching Tsai, Larry S. Metz, Sui-Hing Leung, James S. Ignowski, Kenneth R. Stafford, Ran-Fun Chiu, Richard A. Baugh
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Patent number: 5635935Abstract: A video DAC for driving video displays with reduced power dissipation is presented. This is accomplished using a dual driver circuit connected to a current mirror, the dual driver comprising a strong driver and a weak driver. The dual driver permits switching current between the video load and a dummy load. The current to the dummy load is disabled during periods when the video signal remains steady for a predetermined period of time. The dual driver, using the weak driver, disables the current to the dummy load during video blanking and synchronization periods. This scheme substantially reduces the power dissipation in the DAC.Type: GrantFiled: August 31, 1995Date of Patent: June 3, 1997Assignee: Hewlett-Packard CompanyInventors: James S. Ignowski, Hugh Wallace, Stuart A. Bell
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Patent number: 5061859Abstract: An optical transmitter/receiver pair has an integrated CMOS circuit that provides a current flow to a pre-biased solid state light emitting device (LED) in response to the presence or absence of a digital input signal. The current flow is augmented at the rising and falling edges of the input signal to enhance turn-on and turn-off speed of the LED. The LED is optically coupled to a photodiode that produces a current flow in response to illumination. The photodiode is shielded from spurious electronic noise by a transparent shield and the output of the photodiode is amplified to produce an output voltage, which is connected to a capacitively delayed voltage divider. The voltage divider generates a time delayed threshold voltage connectable along with the output voltage to the inputs of a comparator.Type: GrantFiled: September 13, 1989Date of Patent: October 29, 1991Assignee: Hewlett-Packard CompanyInventors: Ralph E. Lovelace, David J. Gampell, James S. Ignowski