Abstract: A serial communications adapter provides an interface to physical communications ports. A scheduler executing on the adapter schedules tasks at different priority levels, so that time-critical tasks are performed quickly enough to prevent data loss. Data to be transmitted or received through a communications port is stored in buffers on the adapter, and data and command communications between the adapter and the host system are preferably performed over a DMA channel.

Abstract: An I/O bus expansion interface is disclosed which enables an I/O device having an n-bit data bus to be interfaced to an m times n-bit I/O data bus of a host processor. This I/O bus expansion circuit maximizes the computer processor's performance by providing full I/O data bus bandwidth and allowing overlap of processor execution and I/O bus expansion interface circuit operation. This is accomplished by: (1) prefetching multiple control and/or data fields from the I/O device and presenting that information to the host without delay and (2) burst writing multiple fields from the host to the bus expansion interface circuit, without delay of the host, and thereafter making these fields individually available to the I/O device.

Abstract: A terminal communications circuit that provides communication through a bus interface circuit to a network bus in accordance with the predetermined communications procedure, the terminal communications circuit including a communications interchange circuit that exchanges protocol signals with the bus interface circuit in response to commands received from a signal state controller that is resident in the terminal. The communications interchange circuit further provides communications state change information to the signal state controller to indicate the contents of the protocol signals from the bus information circuit. The signal state controller executes one of a plurality of program states to control communications over the network bus in accordance with predetermined communications procedure by providing commands to the communications interchange circuit in acordance with the program state that the signal state controller is currently executing.