Abstract: A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.

Abstract: A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.

Abstract: Described herein is a majority carrier device. Specifically, an exemplary device may comprise source, channel, and drain regions in a thin semiconductor layer, and the source, channel, and drain region may all share a single doping type of varying concentrations. Further, the device may comprise an insulating layer above the channel region and a gate region above the insulating layer, such that the gate modulates the channel. The device described herein may eliminate the parasitic bipolar transistor and the sensitivity to excess minority carrier generation that results from single event effects (SEE) such as heavy ion hits.

Abstract: A differential charge pump with common mode and active regulators is presented. Either type of regulator may be used to improve the performance characteristics of the differential charge pump. The active regulator increases the output range of the differential amplifier. The common mode regulator establishes the common mode voltage of the differential charge pump. The common mode voltage is established independently from external circuitry and does not use a feedback path. The common mode regulator may also be used to establish a mid-rail voltage, which may be used to further improve the output range of the differential amplifier.

Abstract: An apparatus and method for providing a power supply compensted voltage or current is presented. A supply compensated current and voltage source utilizes a differential amplifier connected to a bandgap reference voltage and a scaled power supply voltage. When power supply varies, the differential amplifier regulates a stable compensated output. The output may be a compensated voltage or current. In addition, multiple currents and voltages may be referenced from the differential amplifier. The stable compensated output may be supplied as a reference bias for external circuitry. In addition, the compensated output may be supplied to a voltage controlled oscillator.

Abstract: An apparatus and method for providing a stable gain over wide frequency range in a VCO are presented. A VCO uses a waveform generator along with a bias generator having a frequency select input. The frequency select input is used to adjust the amount of output current and/or gain of the bias generator. The output current of the bias generator determines the frequency of the output of the waveform generator. Multiple bias and waveform generators may be used to expand the frequency range of the VCO. A PLL may be programmed for a variety of output frequencies by using the frequency select input of the VCO.

Abstract: An improved system and method for determining the lock condition of a Phase Locked Loop (PLL) is described. The lock detect circuit generates a fast lock detect signal that may be used to detect a transient loss of lock. The lock detect circuit may also include a phase alignment detect circuit to detect a misalignment in the phase of a reference clock and a feedback clock. Additionally, the lock detect circuit may include a reference clock detect circuit to detect if the reference clock signal is detected. Output signals from all of the above circuits may be communicated to a logic circuit in order to create an enhanced lock detect signal. An extended lock detect signal may also be communicated to the logic circuit.

Abstract: A system and method for generating a reset signal within a Phase Locked Loop (PLL) circuit is described. The reset signal is generated by inputting a reference signal and a lock detect signal into reset circuitry. The reset circuitry within the PLL comprises a series of interconnected latches, or D flip-flops, which are used to create a delay time. The delay time is the amount of time the reset circuit will wait until the reset signal indicates a reset. The reset circuit may also generate a reset signal having a pulse width. The pulse width is determined by the series of interconnected latches. The reset signal may be used to reset a Voltage Controlled Oscillator (VCO) or other circuits within a PLL or it may be used by circuits external to the PLL.

Abstract: An integrated circuit has a buried insulation layer formed over a semiconductor substrate, and a semiconductor mesa formed over the buried insulation layer. A low resistivity guard ring substantially surrounds the semiconductor mesa and is in contact with the semiconductor substrate. The low resistivity guard ring is grounded and isolates the semiconductor mesa from RF signals.

Abstract: The apparatus includes a housing; a plurality of sensors mounted on the housing, each of the sensors including a sensing element and an electrical output connected to said sensing element. The apparatus also includes a plurality of inputs connected to the sensors, respectively, to transmit to the sensors. A circuit is mounted in the housing and in electrical connection with the electrical outputs to provide a common signal conditioner for the sensors.