Abstract: An apparatus is disclosed. The apparatus comprises an instruction mapping table, which includes a plurality of instruction counts and a plurality of instruction pointers each corresponding with one of the instruction counts. Each instruction pointer identifies a next instruction for execution. Further, each instruction count specifies a number of instructions to execute beginning with the next instruction. The apparatus also has a data operation unit adapted to receive a data group and adapted to execute on the received data group the number of instructions specified by a current instruction count of the instruction mapping table beginning with the next instruction identified by a current instruction pointer of the instruction mapping table before proceeding with another data group.

Abstract: A method for loading and executing an indeterminate length shader program. The method includes accessing a first portion of a shader program in graphics memory of a GPU and loading instructions from the first portion into a plurality of stages of the GPU to configure the GPU for program execution. A group of pixels is then processed in accordance with the instructions from the first portion. A second portion of the shader program is accessed in graphics memory of the GPU and instructions from the second portion are loaded into the plurality of stages of the GPU to configure the GPU for program execution. The group of pixels are then processed in accordance with the instructions from the second portion.

Abstract: A method and system for accessing texture data is disclosed. The method includes the step of storing a low resolution version of a block of texture data in a low latency memory and storing a high resolution version of the block of texture data in high latency memory. Upon a request for the high resolution version of the block of texture data, the high resolution version is fetched from the high latency memory to the low latency memory. The low resolution version is subsequently accessed from the low latency memory until the high resolution version is fetched into the low latency memory.

Abstract: A frame buffer is divided into tiles of, for example, 32 by 32 pixels. Triangles (and portions thereof) that are within a given tile are rasterized one triangle at a time into the tile location. This process repeats for each tile in the image frame. A sorting circuit generates control bits representing a vertical order of the vertices of a current triangle. A series of multiplexers vertically sorts the vertices bases on these control bits. A region calculation circuit generates region bits representing a location each of the vertices with respect to the current tile. A trivial discard of the triangle data occurs if the region bits indicate that the entire triangle lies outside of the tile. Subsequently, an initial rasterization starting point is estimated based on the region bits to lower the time needed for the rasterizer to find the first pixel of the current triangle to be assigned values.

Abstract: A computer system that performs motion compensation pixels, the computer system includes a storage device; a memory unit that loads at least one error correction value and at least one reference component into the storage device; and a calculation unit coupled to receive the at least one reference component and the at least one error correction value from the storage device. The calculation unit determines multiple predicted components in parallel and stores the multiple predicted components into the storage device. The arrangement, i.e., field or frame type, of the at least one reference component can differ from the arrangement of the stored multiple predicted components.

Abstract: A graphics processing system includes an initial processing system that receives a command to render an image component polygon and generates parameters for calculating image values for the image component polygon. The graphics processing system also includes a backtrack register capable of storing a pixel location. A rasterization engine scans a pixel span in a selected direction and determines whether the pixel span is to be scanned in a direction opposite the selected direction. The rasterization engine stores a backtrack location in the backtrack register in response to a determination that the pixel span is to be scanned in a direction opposite the selected direction, and stores a location to begin scanning a subsequent pixel span in the backtrack register in response to a determination that a backtrack location is not stored in the backtrack register. The rasterization engine also calculates image values for each pixel in the pixel span in the current scan direction.

Abstract: A novel pipeline processing system includes a parameter bus and a command processor. The command processor receives a command, generates a word in response to the command, and transmits the word on the parameter bus. The word includes information identifying whether the word includes state parameter data and information identifying whether the word includes immediate mode parameter data. A plurality of pipeline stages are positioned along the parameter bus. Each pipeline stage has a state register and a logic block both connected to the parameter bus. The state register receives the word and stores the state parameter data included in the word in response to the information identifying whether the word includes state parameter data. The logic block receives the word and performs a logic operation using state parameter data stored in the state register and the immediate mode parameter data included in the word in response to the information identifying whether the word includes immediate mode parameter data.

Abstract: A circuit is provided for performing a high-precision bilinear interpolation operation. The circuit includes a first interpolation operator for interpolating two operands representing a pair of texels using a weight high component of a weighting value. The first interpolation operator outputs a first result. A second interpolation operator interpolates the two operands representing the pair of texels using a weight low component of the weighting value. The second interpolation operator outputs a second result. A combination operator, coupled to the first and second interpolation operators, combines the first and second results to form a value of higher precision than that yielded by typical circuit implementations for bilinear interpolation operation.

Abstract: A method for rendering polygons in a computer graphics system in which the computer display is divided into a plurality of subregions, and the rasterization process is performed in a micro framebuffer for each subregion, rather than sending raster data for each triangle into the frame buffer. Each polygon undergoes a first stage bounding box intersection test to identify the subregions which are likely to intersect with the polygon. If the number or configuration of intersected subregions exceeds a predetermined threshold requirement, then the polygon undergoes a more precise second stage intersection test to identify which subregions are actually intersected by the polygon. If the number or configuration of intersected subregions is below the threshold requirement, then the control data for the polygon is passed on to each of the identified subregions.

Abstract: A 3-D graphics system combines a software programmed setup processor, a 3-D pipeline, and a software programmed back end processor. The setup processor performs “setup” on polygons for the 3-D pipeline. The 3-D pipeline rasterizes the polygons to create pixels. The back end processor performs back end processing, such as Z-buffering and alpha blending on the pixels. In one embodiment, the throughput of the 3-D graphics system is increased by clusterizing the pixels before back end processing. Specifically, a clusterizer combines pixels into clusters that can be processed by the back end processors without data coherency problems. Furthermore, the pixels are selected for a cluster to minimize memory latency and access times. In some embodiments, clusters are filled with fill addresses by a cluster filler. The filled addresses generated by the cluster filler, do not cause potential hazards in the back end processor.

Abstract: A prefetch buffer architecture includes a prefetch buffer connected to a memory unit via a global bus. A continue detect unit is also connected to the global bus via a global bus interface. The continue detect unit examines prefetched data words for a predetermined bit pattern indicating the possible presence of a “continue” command. The continue detect unit may use one or more comparator circuits to compare each prefetched data word with the predetermined bit pattern. Multiple comparator circuits can be used in parallel to simultaneously examine multiple data words. When the continue detect unit determines that a data word contains the predetermined bit pattern, indicating the likely presence of a “continue” command, the prefetch operation is suspended. The data word likely to contain the “continue” command is stored in the prefetch buffer until it is called by a decode unit, which decodes the continue command.

Abstract: A reconfigurable cache in a signal processor provides a cache optimized for texture mapping. In particular, the reconfigurable cache provides two-banks of memory during one mode of operation and a palettized map under a second mode of operation. In one implementation, the reconfigurable cache optimizes mip-mapping by assigning one texture map in one of the memory banks and a second texture map of a different resolution to the other memory bank. A special mapping pattern ("supertiling") between a graphical image to cache lines minimizes cache misses in texture mapping operations.