Abstract: One embodiment of the present invention provides a flash analog-to-digital converter (ADC) based on a feedforward perceptron. The ADC includes a plurality of N stages to provide N digital signals. The plurality of N stages includes a first stage to provide a sum of an input current, related to a voltage to be converted, and of a reference current. The first stage provides a first digital signal in one of first and second states if the sum has one of first and second signs, respectively. The plurality of N stages further includes i stages, with i=2 . . . N. Each stage i includes an output circuit and 2(i−2) sub-stages coupled to the output circuit. Each sub-stage includes an input and a hidden circuit coupled therebetween. The input circuit is configured to provide a first sum of the input current and of a first reference current. Each hidden circuit provides to the output circuit a second reference current when the first sum has a first sign.

Abstract: A method and apparatus pertains to a mixer. A first differential pair has a first and a second drain lead coupled to a first and a second gate lead respectively. A first transformer is coupled to the first and the second drain lead. A second differential pair has a third and a fourth gate lead coupled to the second and the first gate lead of the first differential pair respectively. A third differential pair has a fifth and a sixth gate lead coupled to the first and the second gate lead of the first differential pair if the mixer is performing as a down converter, and has fifth and sixth drain leads coupled to third and fourth drain leads of the second differential pair respectively. A second transformer is coupled to a first and a second base lead of the second and the third differential pair respectively.

Abstract: A sub-bandgap reference circuit yielding a reference voltage smaller than the bandgap voltage of silicon. The circuit generates a negative temperature coefficient signal V.sub.be and an oppositely tracking (positive temperature coefficient) .DELTA.V.sub.be, and takes the average of two signals related to .DELTA.V.sub.be -V.sub.be to yield a temperature-compensated voltage of one-half the bandgap voltage of silicon. The circuit features an unequal area current mirror feeding the diodes and resistors used to generate the .DELTA.V.sub.be -V.sub.be signals using low supply voltages (less than 1.5 volts). A standard CMOS implementation provides low power consumption at a supply voltage of only 1 volt with a good temperature coefficient. The averaging circuit may be implemented by a continuous time divider or by using switched capacitor techniques. The loop amplifier used in the .DELTA.V.sub.be -V.sub.

Abstract: A programmable circuit is provided. The programmable circuit includes a programmable inverter circuit (PIC) that is configured to receive an input signal and to generate an output signal. The programmable circuit also includes a teaching circuit that is coupled to the PIC. The teaching circuit is configured to compare the output signal of the PIC to a desired output signal. Responsive to this comparison, the teaching circuit is configured to generate a control signal to the PIC. In response to the control signal the PIC is configured to generate the desired output signal.

Abstract: A return-to-zero transmitter includes a one shot circuit, an output circuitry and a timing generator. The one shot circuit is constructed to receive a signal that is indicative of a digital bit and generate an output signal that is indicative of positive and negative edges of the bit. The timing generator receives the output signal of the one shot circuit and causes the output circuitry to generate return-to-zero pulses in response to this signal.

Abstract: The present invention provides a differential amplifier. The differential amplifier includes first and second inputs and an output. The differential amplifier further includes a lateral bipolar transistor. The lateral bipolar transistor includes a well region that has a base region, an emitter region and first and second collector regions. The first and second collector regions are spaced apart from the emitter. The lateral bipolar transistor also includes a first gate, coupled to the first input, to overlay a space between the emitter region and the first collector region. Furthermore, the lateral bipolar transistor includes a second gate, coupled to the second input, to overlay a space between the emitter region and the second collector region. The differential amplifier further includes first and second load devices coupled to the first and second collector regions.

Abstract: An improved bandgap reference circuit that uses ratioed current mirrors to provide loop gain and minimize the offset sensitivity of the loop amplifier. Furthermore, the combination of both current and diode area ratioing provides a larger effective .DELTA.V.sub.be which in turn reduces circuit sensitivities to resistor ratio values. The circuit features a high gain folded cascode amplifier for fast response, and stable start-up and power down modes. The circuit design required no trims, calibrations, or adjustments using a standard submicron digital CMOS fabrication process, and achieved a simulated reference output level with less than 1% drift over time, temperature, and process variations.

Abstract: A method and apparatus of biasing a transistor to perform as a resistive device in an integrated circuit die is disclosed. A base lead of a transistor is coupled to a first lead of the transistor. A voltage is applied to a first lead such that the voltage does not exceed a threshold voltage of the transistor.

Abstract: A sub-bandgap reference circuit yielding a reference voltage smaller than the bandgap voltage of silicon. The circuit generates a negative temperature coefficient signal V.sub.be and an oppositely tracking (positive temperature coefficient) .DELTA.V.sub.be, and takes the average of two signals related to .DELTA.V.sub.be -V.sub.be to yield a temperature-compensated voltage of one-half the bandgap voltage of silicon. The circuit features an unequal area current mirror feeding the diodes and resistors used to generate the .DELTA.V.sub.be -V.sub.be signals using low supply voltages (less than 1.5 volts). A standard CMOS implementation provides low power consumption at a supply voltage of only 1 volt with a good temperature coefficient. The averaging circuit may be implemented by a continuous time divider or by using switched capacitor techniques. The loop amplifier used in the .DELTA.V.sub.be -V.sub.

Abstract: A high data rate communication system that employs an adaptive sectored antenna is disclosed. The high data rate communication system includes an antenna subsystem for receiving and transmitting data. The antenna subsystem is adapted to be spatially steered. A radio frequency transceiver that is coupled to the antenna subsystem and that selectively generates a bit error rate (BER) signal and a receive signal strength indication (RSSI) signal based upon a received antenna training sequence is also provided. The system also includes a beam steering state machine that is coupled to the radio frequency transceiver and that selectively generates a BER.sub.-- PASS signal and an RSSI.sub.-- PASS signal based upon whether the BER signal is in a first logical relationship with a predetermined BER signal and the RSSI signal is in a second logical relationship with a predetermined RSSI signal.

Abstract: A return-to-zero (RZ) receiver is constructed to receive at least two pulses which are distinguishable. The receiver includes two single stage amplifiers. Each different single state amplifier receives a different one of the two pulses and generate signals in response. A summer of the receiver generates an output signal by summing the signals that are generated by the single stage amplifiers.

Abstract: An encoder for encoding binary data bits supplied by a data source into pulse amplitude modulated multilevel symbols. The encoder includes a bit stuffer for receiving the data bits from the data source at a first data bit rate, which at most equals a maximum data bit rate. The bit stuffer then adds descriptive bits to the data bits at a descriptive bit rate, which at most equals a maximum descriptive bit rate. The encoder also includes a multilevel pulse amplitude modulator for receiving the data and descriptive bits from the bit stuffer and for converting the data and descriptive bits into pulse amplitude modulated multilevel symbols. When these multilevel PAM symbols are transmitted, they have a spectral energy characteristic which is below a predetermined low level threshold at a predetermined baseband bandwidth frequency. In addition, these multilevel PAM symbols have a symbol rate (i.e.

Abstract: The present invention provides a bi-directional low pass filtering method and apparatus for attenuating out-of-baseband components of data transmitted from an encoder to a decoder over a transmission medium. In one embodiment of the present invention, the bi-directional low pass filtering apparatus includes a Chebyshev filter that has a first phase response. This Chebyshev filter is coupled to a phase correction circuit, which has a second phase response. This second phase response of the phase correction circuit is designed to oppose the first phase response in order to offset variations in group delay in the data due to the Chebyshev filter.

Abstract: A quasi-adaptive analog equalization method and apparatus for compensating for phase and amplitude degradation of data transmitted over a transmission medium. One embodiment of the present invention includes a first quasi-adaptive equalizer that receives a first set of data, in order to adjust the amplitude and phase of the first set of data to produce a second set of data. The first quasi-adaptive equalizer then supplies the second set of data to a second quasi-adaptive equalizer, which adjusts the amplitude and phase of the second set of data to produce an equalized set of data. As both the first and the second equalizers are quasi-adaptive equalizers, they base the amount of their phase and amplitude compensation on the amplitude of the symbol pulses that the equalization network receives.

Abstract: The present invention provides a bi-directional low pass filtering method and apparatus for attenuating out-of-baseband components of data transmitted from an encoder to a decoder over a transmission medium. In one embodiment of the present invention, the bi-directional low pass filtering apparatus includes a Chebyshev filter that has a first phase response. This Chebyshev filter is coupled to a phase correction circuit, which has a second phase response. This second phase response of the phase correction circuit is designed to oppose the first phase response in order to offset variations in group delay in the data due to the Chebyshev filter.

Abstract: A "true" 16-bit second order Sigma-Delta based converter that has superior analog components and has a programmable comb filter which is coupled to the digital signal processor. This converter comprises a second order Sigma-Delta modulator and a programmable comb filter. The second order Sigma-Delta modulator dramatically attenuates the baseband quantization noise energy (which in turn increases the resolution of the converter), since its superior amplifiers and comparators enable it to oversample and coarsely quantize the analog input signal at a very high sampling frequency of 12 MHz. The amplifiers are class AB OTAs, which have cross coupled NMOS driven input stages, and cascoded output stages. Also, the common mode voltages are the optimal biasing points, and these voltages are kept constant by a differential input stage, by a PV independent temperature dependent current generator, by optimal device size, and by a common mode feedback circuitry.

Abstract: A low power comparator is provided in which a wide common mode range, high resolution and near continuous operation is achieved. The comparator of the present invention employs a wide common mode range with true one millivolt resolution. Furthermore, the comparator is a low power device rendering it readily adaptable to today's portable low power devices. An innovative three stage comparator is described. The first stage receives the two input signals to be compared. A number of innovations are utilized to minimize the offsets and therefore errors in the comparison measurements. More particularly, a transmission gate is provided at the inputs to balance the differential amplifiers employed in the first stage. The balance of the differential output nodes permits fast settling time of the comparator and minimizes voltage stresses which can create offsets. Furthermore, the design incorporates fully symmetric loads and is interdigital for optimum matching and minimum size.

Abstract: A subthreshold sense circuit for clamping an injected current at the input pins of an integrated circuit device before the injected current causes the voltage at the input pins to exceed the supply voltage by more than a diode's ON voltage. The subthreshold sense circuit is driven to operate in the linear region of the FETs. The subthreshold sense circuit of the present invention comprises level shifters, a subthreshold current source, a reference voltage generator, a subthreshold comparator, and a clamping circuit. The subthreshold current source generates a reference drain current to drive the sense circuit of the present invention in the linear region. A level shifter is connected to an input pin to shift the voltage level of the input pin by a subthreshold voltage level. The reference voltage generator provides a reference voltage to be compared with the subthreshold-shifted input voltage.

Abstract: A crystal oscillator comprising a crsytal and an inverter amplifier which utilizes a current mirror to provide a voltage output having a frequency double the frequency of the voltage waveform present in the inverter amplifier.

Abstract: A voltage to current converter circuit manufactured with a MOS process generates a linear reference current over a wide bandwidth and operates with an input signal that varies to either supply rail. A voltage divider network scales an input voltage for conversion to a linear current by a cascode current mirror and a gain resistor. The value of the gain resistor determines the transconductance of the conversion from voltage to current. A second current mirror provides feedback to keep the reference current accurate. An output stage makes available high impedance source and sink current output terminals wherein a source current and a sink current relative to the reference current are provided. Several voltage to current converter circuits may be coupled together to provide a addition, subtraction, multiplication, and other circuit and system functions.