Abstract: A signal processor for a radio frequency (RF) receiver includes a signal processing path having first and second programmable gain amplifiers and first and second offset correction circuits. The first offset correction circuit receives a first digital offset correction word and corrects a first offset of the first programmable gain amplifier by adding a first value corresponding to the first digital offset correction word to an input of the first programmable gain amplifier. The second offset correction circuit receives a second digital offset correction word and corrects a second offset of the second programmable gain amplifier by adding a first value corresponding to the second digital offset correction word to an input of the second programmable gain amplifier. A controller measures offsets of the first and second programmable gain amplifiers during a calibration, and provides the first and second offset correction words in response to the offsets.

Abstract: A signal processor for a radio frequency (RF) receiver includes a signal processing path having first and second programmable gain amplifiers and first and second offset correction circuits. The first offset correction circuit receives a first digital offset correction word and corrects a first offset of the first programmable gain amplifier by adding a first value corresponding to the first digital offset correction word to an input of the first programmable gain amplifier. The second offset correction circuit receives a second digital offset correction word and corrects a second offset of the second programmable gain amplifier by adding a first value corresponding to the second digital offset correction word to an input of the second programmable gain amplifier. A controller measures offsets of the first and second programmable gain amplifiers during a calibration, and provides the first and second offset correction words in response to the offsets.

Abstract: A signal processor for a radio frequency (RF) receiver includes a plurality of distributed signal processing elements, in which a first one receives an input signal and a last one provides an output signal, and a plurality of gain elements interspersed between pairs of said plurality of distributed signal processing elements. The signal processor also includes a like plurality of peak detectors coupled to outputs of corresponding ones of said plurality of gain elements, and an automatic gain controller having inputs coupled to outputs of each of the peak detectors, and outputs coupled to each of the plurality of gain elements. The automatic gain controller independently controls each of the plurality of gain elements to form a like plurality of independent automatic gain control (AGC) loops.

Abstract: A signal processor for a radio frequency (RF) receiver includes a plurality of distributed signal processing elements, in which a first one receives an input signal and a last one provides an output signal, and a plurality of gain elements interspersed between pairs of said plurality of distributed signal processing elements. The signal processor also includes a like plurality of peak detectors coupled to outputs of corresponding ones of said plurality of gain elements, and an automatic gain controller having inputs coupled to outputs of each of the peak detectors, and outputs coupled to each of the plurality of gain elements. The automatic gain controller independently controls each of the plurality of gain elements to form a like plurality of independent automatic gain control (AGC) loops.

Abstract: An adaptive body bias circuit forward or reverse biases bodies of transistors within a compensated circuit as a result of measured parameters of an integrated circuit. The adaptive body bias circuit includes a matched circuit that includes a replica of a signal path within the compensated circuit. The phase of a clock signal at the input to the matched circuit is compared to a phase of a delayed clock signal at the output of the matched circuit. When the delay through the matched circuit varies about one period of the clock signal, a non-zero error value is produced. A bias voltage is generated as a function of the error value, and the bias voltage is applied to the compensated circuit as well as the matched circuit. Integrated circuits can include many adaptive body bias circuits. Bias values can be stored in memories for later use, and bias values within memories can be updated periodically to compensate the circuit over time.

Abstract: An adaptive body bias circuit forward or reverse biases bodies of transistors within a compensated circuit as a result of measured parameters of an integrated circuit. The adaptive body bias circuit includes a matched circuit that includes a replica of a signal path within the compensated circuit. The phase of a clock signal at the input to the matched circuit is compared to a phase of a delayed clock signal at the output of the matched circuit. When the delay through the matched circuit varies about one period of the clock signal, a non-zero error value is produced. A bias voltage is generated as a function of the error value, and the bias voltage is applied to the compensated circuit as well as the matched circuit. Integrated circuits can include many adaptive body bias circuits. Bias values can be stored in memories for later use, and bias values within memories can be updated periodically to compensate the circuit over time.