Abstract: A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.

Abstract: A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a resource power controller. In some embodiments, an integrated circuit includes a resource power controller to control whether a resource is in an up state or a down state. In some embodiments, the resource power controller heuristically estimates when to return the resource to an up state based, at least in part, on an estimate of a gap size.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for chipset determinism to improve validation. In some embodiments, an integrated circuit synchronously receives one or more requests from a processor interconnect, exchanges the requests across an asynchronous interface, and releases a corresponding one or more responses to the processor interconnect on synchronous, deterministic time boundaries with respect to a specified deterministic event.

Abstract: Memory apparatus and methods utilize permuting status patterns. A memory agent may include a pattern generator capable of generating permuting status patterns. A system may include first and second memory agents that send data and permuting status patterns over the same link.

Abstract: Memory apparatus and methods utilize permuting status patterns. A memory agent may include a pattern generator capable of generating permuting status patterns. A system may include first and second memory agents that send data and permuting status patterns over the same link.

Abstract: Method and apparatus provides for testing a device or system with a pattern generator. A series of predetermined test vectors are stored, and, for at least some of the test vectors, an associated predetermined MISR signature. A test vector is applied to a device or system under test and a gold unit in response to a gating signal, the test vector having an associated MISR determined by simulating the expected result vector. In response thereto, the gold unit and the device or system under test each produce a result vector which are compared to detect errors in the performance of the system or device under test. A MISR signature is generated for the result vector from the gold unit. The MISR signature for the result vector is then compared to the MISR associated with the input test vector. If the signatures do not match, further test vectors are prevented from being applied to the device or system under test.

Abstract: A bed extender apparatus adapted for use with a pickup truck bed to functionally enlarge the useable cargo area within the truck bed when a tailgate is in a lowered position. The bed extender includes a center wall which is pivotably mounted to an inner surface of the tailgate, and which can be pivoted into an upright position once the tailgate is moved into a lowered position. A pair of end walls are pivotably secured to opposite ends of the center wall. Each end wall can be pivoted out to a position extending perpendicular to the center wall once the center wall is in its raised or operative position. Each of the end walls can then be secured to an associated one of the vertical walls of the pickup truck bed. A principal advantage of the bed extender is that the end walls and center wall each include a plurality of members which, when the end walls are folded against the center wall, form an extremely compact arrangement which takes up virtually no appreciable cargo space within the pickup truck bed.

Abstract: A bed extender apparatus for use with a truck bed of a vehicle such as a pickup truck. The bed extender includes a center wall having a pair of uprights at opposite ends thereof. A pair of end walls are pivotably coupled to the uprights and can be folded down over the center wall when the bed extender is not in use, or attached to sidewalls of the truck bed to place the bed extender in a bed extending configuration. The center wall is secured to an inside surface of a tailgate of the vehicle by a pair of mounting assemblies. The mounting assemblies allow the bed extender to be quickly slidably detached from the truck bed when not needed. The bed extender can also be installed within the truck bed to provide an article restraining function.

Abstract: A bed extender apparatus for use with a truck bed of a vehicle such as a pickup truck. The bed extender includes a center wall having a pair of uprights at opposite ends thereof. A pair of end walls are pivotably coupled to the uprights and can be folded down over the center wall when the bed extender is not in use, or attached to sidewalls of the truck bed to place the bed extender in a bed extending configuration. The center wall is secured to an inside surface of a tailgate of the vehicle by a pair of mounting assemblies. The mounting assemblies allow the bed extender to be quickly slidably detached from the truck bed when not needed. The bed extender can also be installed within the truck bed to provide an article restraining function.

Abstract: An in-circuit emulator on an integrated circuit chip having an input pin for externally triggering on-chip break mechanisms. A first break logic having a first arm input is connected to an instruction pointer counter (IP counter). The first break logic matches the IP counter to a first instruction execution address. A second break logic having a second arm input is connected to the IP counter. The second break logic matches the IP counter to a second instruction execution address and a third instruction execution address occurring a fixed time interval after the second instruction execution address in a mutistage pipe line of instructions. A sequencer logic connected to the input pin, the first arm input and the second arm input activates the second arm input after the input pin has been active for 1 cycle. The sequencer logic activates the first arm input after the input pin has been active for 2 cycles.

Abstract: An in-circuit emulator trace bus clocking mechanism. A synchronization clock associated with the trace bus is provided. Arrival of a first event on a microprocessor bus to be traced is signified by a transition of a control line. A start of cycle event is detected. A start of cycle signal is generated with respect to the start of cycle event. A two stage pipeline having stage 1 storage elements and stage 2 storage elements are connected to receive data from the microprocessor bus. The start of cycle signal is used to sample data from the microprocessor bus into the stage 1 storage elements. An end of cycle event is detected. An end of cycle signal is generated with reference to the end of cycle event. The end of cycle signal is used to sample data from the stage 1 storage elements into the stage 2 storage elements. The end of cycle signal is also used to sample data appearing on the microprocessor bus at the end of the cycle into the stage 2 storage elements.

Abstract: A micro processor emulator in which a set of core micro processor registers are the communication interface between an external system and a core-ported memory. The registers are connected to a serial scan port for transfer of information between a halted emulation environment and the external system. The serial port includes a command register that receives a jump address to initiate execution of a software monitor. Two special bits are provided in the command register, one that indicates a break, and one that indicates a Fast Break GO. This provides a break mechanism for a micro processor chip which does not have a dedicated memory bus. This break mechanism is the mechanism by which a halt or an asynchronous break is effected. After a fast break, the Fast Break GO mechanism does the action described by one command, and then immediately goes back to emulation without any external processor intervention.

Abstract: A microprocessor is provided with circuitry for receiving JTAG and ICE test control signals through JTAG test ports and for synchronizing the test signals to a chip clock signal. Test signals synchronized to an external JTAG device are processed internally by an ICE of the microprocessor chip once the test signals are synchronized with the chip clock rate. To this end, the microprocessor is provided with a synchronizer which receives the chip clock signal, a JTAG control signal, and a JTAG reset signal, and outputs a synchronized control signal. The synchronizer includes an unclocked SR flip-flop for sampling the JTAG control signal, and two or more DR flip-flops for synchronizing the JTAG control signal to the chip clock signal. The synchronizer may be configured to generate a control signal pulse or a control signal level. The synchronizer is protocol independent, i.e., the clock rate of the JTAG test commands is independent of the chip clock.

Abstract: The electrical protection circuit disclosed comprises a latchup detection circuit, a threshold detector, an oscillator, a charge pump, a switching circuit, a voltage reference and detection circuit, and a signaling circuit. The latchup detection circuit, the threshold detector, the oscillator, the charge pump, and the switching circuit cooperate to provide latchup protection for the CMOS integrated circuit. The switching circuit provides integrated reverse current protection to the CMOS integrated circuit. The voltage reference and detection circuit, the threshold detector, and the signaling circuit provides low voltage protection for the SRAM-based software-downloaded Field Programmable Gate Array of the CMOS integrated circuit.

Abstract: An in-circuit emulator on an integrated circuit chip having an input pin for externally triggering on-chip break mechanisms. A break logic having an arm input is connected to an instruction pointer counter (IP counter). The break logic matches the IP counter to an instruction execution address. A counter is provided that once started runs a period of time and then shuts itself off, the length of the period of time being equal to the amount of time it takes for the break logic to arm after assertion of the arm input. A break logic control is connected to the input pin activates the arm input in response to signals on the input pin. The break logic control also starts the counter.