Abstract: An apparatus multiplies two sequences of digital numbers a.sub.i and b.su, which may represent signal pulses of various amplitudes. A first plurality of t read-only memories (ROMs), have a common input adapted to receive the sequence of numbers a.sub.i, each ROM coding the numbers a.sub.i into a.sub.j,i =a.sub.j modulo m.sub.i, 0.ltoreq.a.sub.j,i .ltoreq.m.sub.i -1. A first plurality of t means, extend the digital signal with zero values, the number of zeroes being determined by the length N of the sequences being convolved. A first plurality of t D/A converters, convert the digital quantity received from the extender into its corresponding analog value.Similar ROMs, extending means, and D/A converters process the sequence numbers b.sub.i.A plurality of t means convolve two input analog signals, one from each of the first and second D/A converters, the output of each convolving means being an analog signal, approximately equal to the convolution (a.sub.j,i) * (b.sub.j,i) modulo m.sub.i.

Abstract: A charge-coupled device (CCD) analog and digital correlator comprises identical modules, each of which is a simple analog CCD correlator with digital input and output. Circuits are included:(1) for injecting charges proportional to the voltage sequences s(n) and r(n), where s(n) refers to the input signal, and r(n) relates to a reference signal, against which the input signal is correlated;(2) for non-destructively sensing and tapping each sample s(n) and r(n);(3) for forming the summation s(n)+r(n);(4) and finally for squaring s(n), r(n), and [s(n)+r(n)] in simple, floating gate MOSFET amplifiers. The amplifiers operate in their saturation region, and have outputs proportional to s.sup.2 (n), r.sup.2 (n), and [s(n)+r(n)].sup.2, which are then fed into a differential amplifier to produce s(n)r(n).

Abstract: Apparatus, useful in signal processing, and which can be used for modulo (2.sup.n -1) addition, subtraction, coding, and decoding, has a plurality of 2n input means: n means for receiving a signal I.sub.0, I.sub.1, . . . , I.sub.n-1, and another n means for receiving a signal J.sub.0, J.sub.1, . . ., J.sub.n-1. A pluraity n of means, connected to the n I signal input means, may switch each input means so that it is connected alternately into one of two connecting points, a first and a second connecting point. A plurality n of means is connected to the n first connecting points, for inverting the polarity of a signal received at its input, the output of the inverting means being connected to its associated second connecting point. A plurality n of three input adding means, has one input connected to the output of the inverting means, and another being connected to an associated means for receiving a J signal, the means adding the two inputs.

Abstract: Apparatus for performing arithmetical calculations on a plurality, N, of ital input signals, utilizing residue class arithmetic, comprising a plurality N of means for coding the N input digital signals into digital modulo m.sub.i integers, K.ltoreq.i.gtoreq.1. K may have a value of approximately 4. A plurality N of means, each means having an input connected to each coding means, converts the digital modulo m.sub.i integers into corresponding analog modulo m.sub.i signals. A plurality N of means performs a mathematical operation on the analog modulo m.sub.i integers, each means having an input connected to a D/A converting means. The means may be a multiplier or a correlator. A plurality N of means, connected to the N operation means, converts the analog modulo m.sub.i integers from the operation means into digital modulo m.sub.i integers. Means, connected to the N A/D converting means, decodes the digital modulo m.sub.i numbers into digital binary outputs.