Abstract: The present invention provides a flexible circuit connector for electrically coupling IC devices to one another in a stacked configuration. Each IC device includes: (1) a package having top, bottom, and peripheral sides; and (2) external leads that extend out from at least one of the peripheral sides. In one embodiment, the flexible circuit connector comprises a plurality of discrete conductors that are adapted to be mounted between the upper side of a first package and the lower side of a second package. The flexible circuit connector also includes distal ends that extend from the conductors. The distal ends are adapted to be electrically connected to external leads from the first and second packages to interconnect with one another predetermined, separate groups of the external leads. In this manner, individual devices within a stack module can be individually accessed from traces on a circuit card.

Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leaded packages into modules that conserve PWB or other board surface area. The present invention can be used to advantage with CSP or leaded packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element IC and a support element IC are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two IC elements.

Abstract: The present invention provides a flexible circuit connector for electrically coupling IC devices to one another in a stacked configuration. Each IC device includes: (1) a package having top, bottom, and peripheral sides; and (2) external leads that extend out from at least one of the peripheral sides. In one embodiment, the flexible circuit connector comprises a plurality of discrete conductors that are adapted to be mounted between the upper side of a first package and the lower side of a second package. The flexible circuit connector also includes distal ends that extend from the conductors. The distal ends are adapted to be electrically connected to external leads from the first and second packages to interconnect with one another predetermined, separate groups of the external leads. In this manner, individual devices within a stack module can be individually accessed from traces on a circuit card.

Abstract: The RAMBUS compatible configuration of the present invention is achieved by stacking one of the two modules in the stacked configuration in an upside-down position with respect to the other. This way, the corresponding electrical leads of each memory module will extend on opposite sides of the stacked package and will be securably connected to vertical rails. The vertical rails are electrically and securably connected to the bonding pads which electrically connect to the RAMBUS signal channel. In this embodiment, the electrical leads of one memory module electrically connect to the signal channel at points located on one side of the stacked package and the electrical leads of the other memory module connect to the signal channel at points located on the opposite side of the stacked package. The resulting distance between the points of contact between corresponding leads of each memory module in the stacked package is sufficient to satisfy the requirements of the RAMBUS signal channel.

Abstract: The present invention provides a method for fabricating modified integrated circuit packages that are ultra-thin and resist warping. The integrated circuit packages are made thinner by removing some of the casing material uniformly from the upper and lower major surfaces of the integrated circuit package. To prevent the resulting ultra-thin integrated circuit package from warping, a thin layer of material with a coefficient of thermal expansion less than that of silicon is mounted to the upper major surface of the package after some of the casing material has been removed uniformly from the upper major surface. Also, a thin layer of material with a coefficient of thermal expansion greater than that of silicon may be mounted to the lower major surface of the package after some of the casing material has been removed uniformly from the lower major surface. The result is an ultra-thin integrated circuit package that is thermally and mechanically balanced to prevent warping.

Abstract: The present invention provides a method for fabricating modified integrated circuit packages that are ultra-thin and resist warping. The integrated circuit packages are made thinner by removing some of the casing material uniformly from the upper and lower major surfaces of the integrated circuit package. To prevent the resulting ultra-thin integrated circuit package from warping, a thin layer of material with a coefficient of thermal expansion less than that of silicon is mounted to the upper major surface of the package after some of the casing material has been removed uniformly from the upper major surface. Also, a thin layer of material with a coefficient of thermal expansion greater than that of silicon may be mounted to the lower major surface of the package after some of the casing material has been removed uniformly from the lower major surface. The result is an ultra-thin integrated circuit package that is thermally and mechanically balanced to prevent warping.

Abstract: Thin and durable level-one and level-two integrated circuit packages are provided. A thin and durable level-one package is achieved in one method involving a molding technique of evenly applying molding compound to an integrated circuit die element. The casing surrounding a die element may be reduced or eliminated in part to thin the level-one package provided any necessary steps are taken to ensure the integrity of the package. Moisture-barriers, as an example, may be provided to the upper and/or lower surfaces of the thin level-one package. Additionally, a thin level-one package may also be constructed with one or more metal layers to prevent warpage. These level-one packages may be aligned in a stacked configuration to form a thin and durable horizontal level-two package. Various thermal conductors may be thermally coupled to the level-two package to help dissipate heat.

Abstract: A method and apparatus for providing a multiple-element ultra high density level-two integrated circuit modular package utilizing a temporary manufacturing fixture to achieve a stack of individual thin ultra high density integrated circuit packages.

Abstract: Thin and durable level-one and level-two integrated circuit packages are provided. Moisture-barriers may be provided to upper and/or lower surfaces of the thin level-one package. Additionally, a thin level-one package may be constructed with one or more metal layers to prevent warpage. These level-one packages are aligned in a stacked configuration to form a thin and durable horizontal level-two package. Various thermal conductors are thermally coupled to the level-two package to help dissipate heat.

Abstract: The memory addressing system of the present invention incorporates industry standard features for compatibility and adds the capability of using high-density module memory boards exclusively or in combination with current or next generation standard memory modules without increasing system power requirements. The system provides a plurality of standardized memory module circuit board sockets that are electrically connected so as to provide address decoded RAS signals in addition to the standard row and column addressing signals.

Abstract: Thin and durable level-one and level-two integrated circuit packages are provided. A thin and durable level-one package is achieved in one method involving a molding technique of evenly applying molding compound to an integrated circuit die element. The casing surrounding a die element may be reduced or eliminated in part to thin the level-one package provided any necessary steps are taken to ensure the integrity of the package. Moisture-barriers, as an example, may be provided to the upper and/or lower surfaces of the thin level-one package. Additionally, a thin level-one package may also be constructed with one or more metal layers to prevent warpage. These level-one packages may be aligned in a stacked configuration to form a thin and durable horizontal level-two package. Various thermal conductors may be thermally coupled to the level-two package to help dissipate heat.

Abstract: The present invention provides a method for fabricating modified integrated circuit packages that are ultra-thin and resist warping. The integrated circuit packages are made thinner by removing some of the casing material uniformly from the upper and lower major surfaces of the integrated circuit package. To prevent the resulting ultra-thin integrated circuit package from warping, a thin layer of material with a coefficient of thermal expansion less than that of silicon is mounted to the upper major surface of the package after some of the casing material has been removed uniformly from the upper major surface. Also, a thin layer of material with a coefficient of thermal expansion greater than that of silicon may be mounted to the lower major surface of the package after some of the casing material has been removed uniformly from the lower major surface. The result is an ultra-thin integrated circuit package that is thermally and mechanically balanced to prevent warping.

Abstract: The present invention provides a method for fabricating modified integrated circuit packages that are ultra-thin and resist warping. The integrated circuit packages are made thinner by removing some of the casing material uniformly from the upper and lower major surfaces of the integrated circuit package. To prevent the resulting ultra-thin integrated circuit package from warping, a thin layer of material with a coefficient of thermal expansion less than that of silicon is mounted to the upper major surface of the package after some of the casing material has been removed uniformly from the upper major surface. Also, a thin layer of material with a coefficient of thermal expansion greater than that of silicon may be mounted to the lower major surface of the package after some of the casing material has been removed uniformly from the lower major surface and after a layer of adhesive has been applied to the thin layer of material and cured.

Abstract: An inexpensive, easily assembled electrical connector provides simultaneous secure connection of both center and outer conductors in a bundle of coaxial wires and includes a conductive housing having a cylindrical bore for each wire of the bundled cable. Each bore has a small diameter constriction adjacent a rear surface of the housing and a dielectric insert is disposed in each cylindrical bore from the constriction forward to a front surface of the housing. A conductive pin is attached to the end of each coaxial wire and is inserted into one of the inserts, carrying the coaxial cable into the rear end of a housing bore until the outer conductor meets the constriction, electrically coupling all of the outer conductors to the conductive housing and precisely positioning each of the center conductors relative to a mating center conductor. A connector assembly has a pair of mating connectors that may be electrically connected.

Abstract: A low cost high signal frequency multiwire cable and method of manufacture includes a stack of wire pairs fan folded from a flat ribbon cable to form columnated wire pair layers. The flat ribbon cable is folded together with a flexible conductive shield which extends around and between each layer to provide high quality signal isolation of each layer. The cable may be clad with multiple layers providing additional shielding and physical protection.

Abstract: The memory addressing system of the present invention incorporates industry standard features for compatibility and adds the capability of using high-density module memory boards exclusively or in combination with current or next generation standard memory modules without increasing system power requirements. The system provides a plurality of standardized memory module circuit board sockets that are electrically connected so as to provide address decoded RAS signals in addition to the standard row and column addressing signals.