Abstract: A method for recovering the clock in an ADSL (asymmetric digital subscriber line) communication system at the receiver to match the frequency of the transmitted signal. A digital phase locked loop (DPLL) based clock is used to adjust the frequency of data read accesses from a FIFO (first-in first-out) memory (26) in a transceiver unit. The frequency is adjusted according to a predetermined offset value, where the offset value indicates the relative difference between a read location in the FIFO memory (26) and a write location. The predetermined offset value defines an operating point or nominal data location in the FIFO memory (26). A FIFO phase detector (31) determines and affects the frequency adjustment to maintain the FIFO memory at approximately the operating point. One embodiment provides clock recovery for a received ADSL subchannel and a means to recover a 16 kHz clock for a channel control.

Abstract: An interface (50) for a transceiver (5) for use in an asymmetric digital subscriber line (ADSL) system includes a routing table (200) which includes addresses of locations in a frame memory (150). When the transceiver (5) is operated as a central office transmitter input port data is received from several input ports. The routing table (200) addresses assign locations in the frame memory (150), corresponding to channels in the ADSL frame, which may be arbitrarily assigned. A control circuit (148) services the input ports by transferring data between the input ports and the address selected by the routing table (200). When operated as a remote terminal receiver, the transceiver (5) uses a routing table addressing the system except that the ports become output ports and frame memory (150) locations provide data to the output ports.