Abstract: An approach is provided for fabricating probe elements for probe card assemblies. Embodiments of the invention include using a reusable substrate, a reusable substrate with layered probe elements and a reusable substrate with a passive layer made of a material that does not adhere well to probe elements formed thereon. Examples of probe elements include, without limitation, a cantilever probe element, a vertically-oriented probe element, and portions of probe elements, e.g., a beam element of a cantilever probe element. Probe elements, or portions of probe elements, may be formed using any of a number of electroforming or plating processes such as, for example, plating using masking techniques, e.g., using lithographic techniques such as photolithography, stereolithography, X-ray lithography, etc.

Abstract: A method of processing a semiconductor device is provided. The method includes providing a semiconductor device supported by a carrier structure. The carrier structure defines a plurality of vias from a first surface of the carrier structure adjacent the semiconductor device to a second surface of the carrier structure. The method also includes extending a conductor through one of the vias such that a first end of the conductor at least partially extends below the second surface. The method also includes electrically coupling another portion of the conductor to a portion of the semiconductor device.

Abstract: An approach is provided for fabricating probe elements for probe card assemblies. Embodiments of the invention include using a reusable substrate, a reusable substrate with layered probe elements and a reusable substrate with a passive layer made of a material that does not adhere well to probe elements formed thereon. Examples of probe elements include, without limitation, a cantilever probe element, a vertically-oriented probe element, and portions of probe elements, e.g., a beam element of a cantilever probe element. Probe elements, or portions of probe elements, may be formed using any of a number of electroforming or plating processes such as, for example, plating using masking techniques, e.g., using lithographic techniques such as photolithography, stereolithography, X-ray lithography, etc.

Abstract: An optoelectronic sensor is attached to an optically transparent substrate, such as glass, and encapsulated to form an optoelectronic device. An optical assembly can be mounted opposite the optoelectronic sensor. Filters and refractive index matching materials may be included between the optoelectronic sensor and the optically transparent substrate.

Abstract: A method of processing a semiconductor device is provided. The method includes providing a semiconductor device supported by a carrier structure. The carrier structure defines a plurality of vias from a first surface of the carrier structure adjacent the semiconductor device to a second surface of the carrier structure. The method also includes extending a conductor through one of the vias such that a first end of the conductor at least partially extends below the second surface. The method also includes electrically coupling another portion of the conductor to a portion of the semiconductor device.

Abstract: An optoelectronic sensor is attached to an optically transparent substrate, such as glass, and encapsulated to form an optoelectronic device. An optical assembly can be mounted opposite the optoelectronic sensor. Filters and refractive index matching materials may be included between the optoelectronic sensor and the optically transparent substrate.

Abstract: A nickel/palladium/gold metallization stack is formed upon connection pads of integrated circuits at the wafer level through an electroless plating method. The metallization stack can be formed over copper or aluminum interconnect pads; the lower nickel layer bonds securely to the copper or aluminum interconnect pads, while the intermediate palladium layer serves as a diffusion barrier for preventing the nickel from out-diffusing during subsequent thermal cycles. The upper gold layer adheres to the palladium and readily receives a variety of interconnect elements, including gold bumps, gold wire bonds, solder bumps, and nickel bumps. The electroless plating process permits connection pads to be formed using fine geometries, and allows adjacent connection pads to be formed within 5 micrometers of each other.

Abstract: A nickel/palladium/gold metallization stack is formed upon connection pads of integrated circuits at the wafer level through an electroless plating method. The metallization stack can be formed over copper or aluminum interconnect pads; the lower nickel layer bonds securely to the copper or aluminum interconnect pads, while the intermediate palladium layer serves as a diffusion barrier for preventing the nickel from out-diffusing during subsequent thermal cycles. The upper gold layer adheres to the palladium and readily receives a variety of interconnect elements, including gold bumps, gold wire bonds, solder bumps, and nickel bumps. The electroless plating process permits connection pads to be formed using fine geometries, and allows adjacent connection pads to be formed within 5 micrometers of each other.

Abstract: A method is provided for forming planar multilevel metallization of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Multilevel metallization is achieved through a planar process at each layer to allow for minimum widths of lines and vias and minimal lateral spacing between lines. Conductive lines and contacts are formed before planarization to further achieve good step coverage. A first metallization layer is formed by depositing aluminum over the integrated circuit, patterning and etching to form metal interconnect lines. Regions of planar insulating material are then formed between the metal lines. Another layer of aluminum is deposited and etched to form metal vias over selected portions of the metal lines. This layer of aluminum is patterned with a reverse pattern of that used to pattern the metal lines. Again, regions of planar insulating material are formed between the metal vias.

Abstract: A method is provided for forming planar multilevel metallization of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Multilevel metallization is achieved through a planar process at each layer to allow for minimum widths of lines and vias and minimal lateral spacing between lines. Conductive lines and contacts are formed before planarization to further achieve good step coverage. A first metallization layer is formed by depositing aluminum over the integrated circuit, patterning and etching to form metal interconnect lines. Regions of planar insulating material are then formed between the metal lines. Another layer of aluminum is deposited and etched to form metal vias over selected portions of the metal lines. This layer of aluminum is patterned with a reverse pattern of that used to pattern the metal lines. Again, regions of planar insulating material are formed between the metal vias.