Patents by Inventor Jamory Hawkins
Jamory Hawkins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11436013Abstract: A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.Type: GrantFiled: March 26, 2020Date of Patent: September 6, 2022Assignee: International Business Machines CorporationInventors: Omesh Bajaj, Kevin Barnett, Debapriya Chatterjee, Bryant Cockcroft, Jamory Hawkins, Lance G. Hehenberger, Jeffrey Kellington, Paul Lecocq, Lawrence Leitner, Tharunachalam Pindicura, John A. Schumann, Paul K. Umbarger, Karen Yokum
-
Patent number: 11403109Abstract: A computer system, processor, and method for processing information is disclosed that includes reading out a plurality of entries in a history buffer prior to initiating a flush recovery process; initiating the flush recovery process; determining which of the history buffer entries read out of the history buffer should be recovered; and sending information associated with the history buffer entries to be recovered to one or more history buffer recovery ports. In one or more embodiments, the history buffer entries are continually read out in response to a processor and history buffer entries read out from the history buffer are directed to a specific history buffer recovery port associated with a mapper of a specific logical register.Type: GrantFiled: December 5, 2018Date of Patent: August 2, 2022Assignee: International Business Machines CorporationInventors: Steven J. Battle, Khandker Nabil Adeeb, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Jamory Hawkins, Dung Q. Nguyen
-
Patent number: 10740140Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor for processing instructions, the processor having a history buffer having a plurality of entries for storing information associated with a processor instruction evicted from a logical register, the history buffer having at least one recovery port; a logical register mapper for recovering information from the history buffer, the mapper having restore ports to recover information from the history buffer; and a restore multiplexor configured to receive as inputs information from one or more of the history buffer recovery ports, and configured to output information to one or more of the logical register mapper restore ports. The processor, system and/or method configured to improve flush recovery bandwidth.Type: GrantFiled: November 16, 2018Date of Patent: August 11, 2020Assignee: International Business Machines CorporationInventors: Steven J. Battle, Khandker Nabil Adeeb, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Jamory Hawkins, Dung Q. Nguyen
-
Publication number: 20200225952Abstract: A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.Type: ApplicationFiled: March 26, 2020Publication date: July 16, 2020Inventors: Omesh Bajaj, Kevin Barnett, Debapriya Chatterjee, Bryant Cockcroft, Jamory Hawkins, Lance G. Hehenberger, Jeffrey Kellington, Paul Lecocq, Lawrence Leitner, Tharunachalam Pindicura, John A. Schumann, Paul K. Umbarger, Karen Yokum
-
Patent number: 10705843Abstract: A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.Type: GrantFiled: December 21, 2017Date of Patent: July 7, 2020Assignee: International Business Machines CorporationInventors: Omesh Bajaj, Kevin Barnett, Debapriya Chatterjee, Bryant Cockcroft, Jamory Hawkins, Lance G. Hehenberger, Jeffrey Kellington, Paul Lecocq, Lawrence Leitner, Tharunachalam Pindicura, John A. Schumann, Paul K. Umbarger, Karen Yokum
-
Publication number: 20200183701Abstract: A computer system, processor, and method for processing information is disclosed that includes reading out a plurality of entries in a history buffer prior to initiating a flush recovery process; initiating the flush recovery process; determining which of the history buffer entries read out of the history buffer should be recovered; and sending information associated with the history buffer entries to be recovered to one or more history buffer recovery ports. In one or more embodiments, the history buffer entries are continually read out in response to a processor and history buffer entries read out from the history buffer are directed to a specific history buffer recovery port associated with a mapper of a specific logical register.Type: ApplicationFiled: December 5, 2018Publication date: June 11, 2020Inventors: Steven J. Battle, Khandker Nabil Adeeb, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Jamory Hawkins, Dung Q. Nguyen
-
Publication number: 20200159564Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor for processing instructions, the processor having a history buffer having a plurality of entries for storing information associated with a processor instruction evicted from a logical register, the history buffer having a at least one recovery port; a logical register mapper for recovering information from the history buffer, the mapper having restore ports to recover information from the history buffer; and a restore multiplexor configured to receive as inputs information from one or more of the history buffer recovery ports, and configured to output information to one or more of the logical register mapper restore ports. The processor, system and/or method configured to improve flush recovery bandwidth.Type: ApplicationFiled: November 16, 2018Publication date: May 21, 2020Inventors: Steven J. Battle, Khandker Nabil Adeeb, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Jamory Hawkins, Dung Q. Nguyen
-
Publication number: 20190196816Abstract: A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.Type: ApplicationFiled: December 21, 2017Publication date: June 27, 2019Inventors: Omesh Bajaj, Kevin Barnett, Debapriya Chatterjee, Bryant Cockcroft, Jamory Hawkins, Lance G. Hehenberger, Jeffrey Kellington, Paul Lecocq, Lawrence Leitner, Tharunachalam Pindicura, John A. Schumann, Paul K. Umbarger, Karen Yokum