Abstract: Method, apparatus and program product for communicating from a node to a communications device. A Hardware Abstraction Layer (HAL) provides functions which can be called from user space in a node to access the communications device. An instance of HAL is created in the node. Device specific characteristics from the communications device and a pointer pointing to HAL functions for accessing the communications device are obtained by HAL. HAL then opens multiple ports on the communications device using the functions pointed to by the pointer, and messages are sent between the node and the communications device. The messages thus sent are optimized with respect to the communications device as determined by the obtained device specific characteristics. Multiple processes and protocol stacks may be associated with each port in a single instance of HAL. A further embodiment provides that multiple virtual ports may be associated with a port, with a multiple protocol stacks associated with each virtual port.

Abstract: A method, apparatus and program product for detecting a communication event in a distributed parallel data processing system in which a message is sent from an origin to a target. A low-level application programming interface (LAPI) is provided which has an operation for associating a counter with a communication event to be detected. The LAPI increments the counter upon the occurrence of the communication event. The number in the counter is monitored, and when the number increases, the event is detected. A completion counter in the origin is associated with the completion of a message being sent from the origin to the target. When the message is completed, LAPI increments the completion counter such that monitoring the completion counter detects the completion of the message. The completion counter may be used to insure that a first message has been sent from the origin to the target and completed before a second message is sent.

Abstract: A method, apparatus and program product for message communication in a distributed parallel data processing system. A user message is sent from a sender to a receiver. The user message contains user data and a pointer to a header handler routine. The header handler routine includes a first pointer to a target user buffer and a second pointer to a completion routine. When the user message is received, a low level application program interface (LAPI) is informed which invokes the header handler routines which returns the first and second pointers. LAPI then transfers the user data to the user buffer indicated by the header handler routine, and invokes the completion routine indicated by the header handler routine to complete the transfer of the user message to the receiver.

Abstract: A cache bypass mechanism automatically avoids caching of data for instructions whose data references, for whatever reason, exhibit low cache hit ratio. The mechanism keeps a record of an instruction's behavior in the immediate past, and this record is used to decide whether its future references should be cached or not. If an instruction is experiencing bad cache hit ratio, it is marked as non-cacheable, and its data references are made to bypass the cache. This avoids the additional penalty of unnecessarily fetching the remaining words in the line, reduces the demand on the memory bandwidth, avoids flushing the cache of useful data and, in parallel processing environments, prevents line thrashing. The cache management scheme is automatic and requires no compiler or user intervention.

Abstract: A dynamic address translation (DAT) mechanism which supports virtual memory pages of different sizes with minimal hardware and design impact. The dynamic look-aside table (DLAT) is modified to allow the addition of a second page size to system architecture. In one approach, the DLAT is divided into two sections, one for small (4KB) pages and one for large (1MB) pages. A steering table indicates whether the segment last contained 4KB pages or a 1MB page. As each segment is translated by the DAT mechanism, the page size (1MB or 4KB) contained in the segment is known, and this information is used to select the address bus used for indexing the DLAT. In an alternative approach, the DLAT is not divided into sections; rather, it can interchangeably hold/test/select either of the two different formats in any entry. The steering table dynamically changes the way in which the DLAT is addressed and selects the bits of the entry to be used in the translation.

Abstract: A dynamic address translation mechanism uses a single translation look aside buffer (TLB) facility for pages of various sizes. The single TLB is supported by a small amount of special hardware. This hardware includes logic for detecting a page size prior to translation and generating a mask. The logic selects a set of virtual address bits for addressing the entries in the TLB. Parts of the virtual address are masked and merged with the address read out of the TLB to form the real address.

Abstract: A technique and a mechanism accurately determines the correct prefetch line for loops with strides of 1, N, or a combination of stride values. Stride registers are used to assist in prefetching. Furthermore, stride register values can be used to specify "cacheability" of data on an object by object basis to prevent "cache flushing". The compiler uses a new instruction, "MOVE GPR TO STRIDE REGISTER", prior to a loop to insert the "calculated stride value(s)" into the stride register(s) associated with the index register(s) which will be incremented by that stride value. At the end of the loop, a second new instruction, "CLEAR STRIDE REGISTER SET", is used to place a value of zero in all of the stride registers to inhibit prefetching of data which would most likely not be used. A zero value in the stride registers inhibits prefetching. Non-zero values in the stride registers clearly mark the execution of a loop, which is where prefetching makes the most sense.

Abstract: A memory system for a high performance data processing system comprises a plurality of memory modules. In the preferred embodiment, there are 2.sup.N +1 memory modules. In a specific example, there are 65 such modules. When all 65 modules are enabled, a real-to-physical translation unit generates logical module addresses from 0 to 64 using modulo 65 calculations. Once a module failure is detected, the translation unit maps the real addresses to logical module addresses from 0 to 63 by performing modulo 64 calculations. The contiguous set of logical module addresses are then mapped to a set of physical module addresses which do not include the failed module.