Patents by Inventor Jan-Her Horng

Jan-Her Horng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7105379
    Abstract: A method of protecting a bond pad during die-sawing comprising the following steps. A substrate having a bond pad formed thereover is provided. A bond pad protection layer is formed over the bond pad. The substrate is die-sawed and the bond pad protection layer is removed by heating.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: September 12, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Haw Tsao, Jan-Her Horng, Cheng-Chung Chang
  • Publication number: 20050245050
    Abstract: A method of protecting a bond pad during die-sawing comprising the following steps. A substrate having a bond pad formed thereover is provided. A bond pad protection layer is formed over the bond pad. The substrate is die-sawed and the bond pad protection layer is removed by heating.
    Type: Application
    Filed: April 28, 2004
    Publication date: November 3, 2005
    Inventors: Pei-Haw Tsao, Jan-Her Horng, Cheng-Chung Chang
  • Patent number: 5942800
    Abstract: A method for forming a chess-board patterned bond pad structure with stress buffered characteristics and the bond pad structure formed are disclosed. In one method, a multiplicity of field oxide regions are first formed in the surface of a silicon substrate. A conductive layer such as polycide is then deposited and formed on the substrate to form a stepped surface with a metal layer subsequently deposited on top of the conductive layer to form a bond pad. The stepped structure reproduced on the metal layer serves to distribute bonding stresses during a wire bonding process such that bond pad lift-off defects are substantially eliminated. In another method, the conductive layer is first formed into conductive gates with insulating sidewalls formed subsequently. Similarly stepped surface on a metal layer can be obtained to realize the stress buffered characteristics of the novel method.
    Type: Grant
    Filed: June 22, 1998
    Date of Patent: August 24, 1999
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ho-Yin Yiu, Lin-June Wu, Bor-Cheng Chen, Jan-Her Horng