Abstract: A device comprising a stack of layers defining one or more electronic elements, wherein the stack comprises at least: one or more semiconductor channels; a dielectric; a first conductor pattern defining one or more coupling conductors, wherein the one or more coupling conductors are capacitively coupled to the one or one or more semiconductor channels via the dielectric; a planarisation layer; a second conductor pattern defining one or more routing conductors, wherein the second conductor pattern is in contact with the first conductor pattern via through holes in at least the planarisation layer, and wherein the semiconductor channel regions are at least partly outside the through hole regions.

Abstract: A display device including a liquid crystal cell having liquid crystal material contained between a control component having at least an organic semiconductor layer supported on a first support film, and a counter component having a second support film. The device further includes a first polarising filter component on the opposite side of the control component to the liquid crystal material and a second polarising filter component on the opposite side of the counter component to the liquid crystal material. The device also includes one or more oxygen-permeable, self-supportable films having a total thickness of at least 185 microns between the first polarising filter component and the control component and/or between the second polarising filter component and the counter component.

Abstract: A technique comprising: providing on an outer side of a support film of a liquid crystal cell one or more first components having an oxygen transmission rate (OTR) at least 100,000 times lower than said support film of the liquid crystal cell; wherein the method further comprises interposing a preprepared oxygen-permeable adhesive film between said support film of the liquid crystal cell and an innermost one of said one or more first components; wherein the pre-prepared oxygen-permeable adhesive film has a thickness greater than another adhesive film provided on said outer side of said support film outside of said innermost one of said one or more first components.

Abstract: A device including a stack of layers defining a first conductor pattern at a first level of the stack and one or more semiconductor channels in respective regions, connecting a pair of parts of the first conductor pattern, and capacitively coupled via a dielectric to a coupling conductor of a second conductor pattern at a second level of the stack. The stack includes at least two insulator patterns over which the first level or second level conductor patterns is formed. A first insulator pattern occupies one or more semiconductor channel regions to provide the dielectric. The second insulator pattern defines one or more windows in the one or more semiconductor channel regions through which the second conductor pattern contacts the first insulator pattern other than via the second insulator pattern. The second insulator pattern overlaps the first insulator pattern outside the one or more semiconductor channel regions.

Abstract: A device comprising a liquid crystal cell, wherein the liquid crystal cell comprises LC material contained between opposing surfaces of two components; wherein the opposing surfaces intermesh in at least one or more regions of the LC cell.

Abstract: A technique, comprising: forming in situ on a support substrate: a first metal layer; a light-absorbing layer after the first metal layer; a conductor pattern after the light-absorbing layer; and a semiconductor layer after the conductor pattern; patterning the semiconductor layer using a resist mask to form a semiconductor pattern defining one or more semiconductor channels of one or more semiconductor devices; and patterning the light-absorbing layer using the resist mask and the conductor pattern, so as to selectively retain the light-absorbing layer in regions that are occupied by at least one of the resist mask and the conductor pattern.

Abstract: A technique comprising: forming an insulator over a first conductor pattern; patterning the insulator to form an insulator pattern which exposes the first conductor pattern in one or more via regions; forming a second conductor pattern over the insulator pattern, which second conductor pattern contacts said first conductor pattern in said one or more via regions; creating a more even topographic profile in said one or more via regions, with the second conductor pattern exposed outside the one or more via regions; forming a semiconductor (24) over the second conductor pattern for charge carrier transfer between the second conductor pattern and the semiconductor; and depositing a third conductor (26) over the semiconductor, for charge carrier transfer between the third conductor (26) and the semiconductor (24).

Abstract: A technique, comprising: forming in situ on a support substrate: a first metal layer; a light-absorbing layer after the first metal layer; a conductor pattern after the light-absorbing layer; and a semiconductor layer after the conductor pattern; patterning the semiconductor layer using a resist mask to form a semiconductor pattern defining one or more semiconductor channels of one or more semiconductor devices; and patterning the light-absorbing layer using the resist mask and the conductor pattern, so as to selectively retain the light-absorbing layer in regions that are occupied by at least one of the resist mask and the conductor pattern.

Abstract: A device comprising a stack of layers defining one or more electronic elements, wherein the stack comprises at least: one or more semiconductor channels; a dielectric; a first conductor pattern defining one or more coupling conductors, wherein the one or more coupling conductors are capacitively coupled to the one or one or more semiconductor channels via the dielectric; a planarisation layer; a second conductor pattern defining one or more routing conductors, wherein the second conductor pattern is in contact with the first conductor pattern via through holes in at least the planarisation layer, and wherein the semiconductor channel regions are at least partly outside the through hole regions.

Abstract: A technique of producing a stack defining a plurality of TFTs including at least source/drain electrodes and addressing lines at a source/drain level, wherein the method comprises: forming a patterned source/drain level stack comprising at least a first layer over the support substrate and a second layer over the first layer, to define at least said source/drain electrodes and said addressing lines; depositing semiconductor channel material over at least said source/drain electrodes and said addressing lines; and patterning the layer of semiconductor channel material by a patterning process; wherein the material of the first layer is more resistant to removal by said patterning process than the material of said second layer.

Abstract: A technique comprising: providing on an outer side of a support film of a liquid crystal cell one or more first components having an oxygen transmission rate (OTR) at least 100,000 times lower than said support film of the liquid crystal cell; wherein the method further comprises interposing a preprepared oxygen-permeable adhesive film between said support film of the liquid crystal cell and an innermost one of said one or more first components; wherein the pre-prepared oxygen-permeable adhesive film has a thickness greater than another adhesive film provided on said outer side of said support film outside of said innermost one of said one or more first components.

Abstract: A technique, comprising: assembling together two liquid crystal half-cells; wherein at least one of the two half-cells comprises a support film and an array of spacer structures formed in situ on the support film; and wherein the assembling comprises pressing together the two half-cells with pre-prepared spacer elements dispensed onto at least one of the two half-cells over at least an area shared with the array of spacer structures; wherein the spacer elements provide primary control of the size of a cell gap between the two half-cells, and the spacer structures function to resist compression of the spacer elements.

Abstract: A device including a stack of layers defining a first conductor pattern at a first level of the stack and one or more semiconductor channels in respective regions, connecting a pair of parts of the first conductor pattern, and capacitively coupled via a dielectric to a coupling conductor of a second conductor pattern at a second level of the stack. The stack includes at least two insulator patterns over which the first level or second level conductor patterns is formed. A first insulator pattern occupies one or more semiconductor channel regions to provide the dielectric. The second insulator pattern defines one or more windows in the one or more semiconductor channel regions through which the second conductor pattern contacts the first insulator pattern other than via the second insulator pattern. The second insulator pattern overlaps the first insulator pattern outside the one or more semiconductor channel regions.

Abstract: A technique comprising: forming a first conductor pattern at least partly defining source and/or drain conductors for one or more thin film transistor devices; exposing the conductor pattern to a reactive halogen species; and depositing organic semiconductor channel material directly over the exposed first conductor pattern to provide one or more semiconductor channels between source and drain conductors of the exposed first conductor pattern.

Abstract: A technique comprising: processing a plastics film in situ on a first carrier; thereafter removing the processed plastics film from the first carrier; subjecting the processed plastics film to one or more quality checks; and following a determination that the processed plastics film meets one or more predetermined quality criteria, bonding the processed plastics film to a second carrier; further processing the processed plastics film in situ on the second carrier; and thereafter debonding the further processed plastics film from the second carrier using a process having a higher yield than that of the process of removing the processed plastics film from the first carrier.

Abstract: Method for forming an organic polymer insulator over a first conductor pattern defining a first level of conductors for a thin-film transistor device. A first conductor layer is formed over the organic polymer insulator and a second conductor layer formed over the first conductor layer. The second conductor layer is patterned to define a second level of conductors by exposing the second conductor layer to liquid etchant in selected regions to form a second conductor pattern. The first conductor layer may be located in the selected regions and the first conductor layer and the organic polymer insulator may comprise surface materials that exhibit a substantially zero etch rate for the liquid etchant. The first conductor layer may be less permeable to the liquid etchant than the organic polymer insulator and/or more resistant to damage by the liquid etchant than the organic polymer insulator may be patterned.

Abstract: A technique comprising: forming an insulator over a first conductor pattern; patterning the insulator to form an insulator pattern which exposes the first conductor pattern in one or more via regions; forming a second conductor pattern over the insulator pattern, which second conductor pattern contacts said first conductor pattern in said one or more via regions; creating a more even topographic profile in said one or more via regions, with the second conductor pattern exposed outside the one or more via regions; forming a semiconductor (24) over the second conductor pattern for charge carrier transfer between the second conductor pattern and the semiconductor; and depositing a third conductor (26) over the semiconductor, for charge carrier transfer between the third conductor (26) and the semiconductor (24).

Abstract: A technique comprising: depositing a first layer comprising a precursor to a cross-linked polymer on a substrate comprising at least a semiconductor material that provides one or more semiconductor channels for one or more transistors, wherein said first layer provides at least part of a gate dielectric for said one or more transistors; and exposing the first layer to an argon plasma to produce the cross-linked polymer from the precursor.

Abstract: A method of forming a stack of layers defining one or more electronic devices, the method comprising: depositing a first thickness of curable, dielectric or dielectric precursor material over an area of a workpiece; thereafter exposing the workpiece to curing conditions at least over said area of said workpiece; and without any intermediate patterning operation, thereafter depositing a second thickness of said curable material over said area of said workpiece; and thereafter again exposing the workpiece to curing conditions at least over said area of said workpiece.

Abstract: An electronic or optoelectronic device including a semiconductor layer, wherein the semiconductor layer comprises at least a semiconductive organic material, water species, and at least one additive in an amount of at least 0.1% by weight relative to the semiconductive organic material, which additive at least partly negates a charge carrier trapping effect caused by the water species on the semiconductive organic material.