Patents by Inventor Jan Lanik

Jan Lanik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for formal fault propagation analysis
    Patent number: 11816410
    Abstract: A system and method are disclosed for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: November 14, 2023
    Assignee: Siemens Electronic Design Automation Gmbh
    Inventors: Dominik Strasser, Jörg Grosse, Jan Lanik, Raik Brinkmann
  • SYSTEM AND METHOD FOR FORMAL FAULT PROPAGATION ANALYSIS
    Publication number: 20220414306
    Abstract: A system and method are disclosed for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.
    Type: Application
    Filed: August 30, 2022
    Publication date: December 29, 2022
    Inventors: Dominik Strasser, Jörg Grosse, Jan Lanik, Raik Brinkmann
  • System and method for formal fault propagation analysis
    Patent number: 11520963
    Abstract: A system and method for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: December 6, 2022
    Assignee: ONESPIN SOLUTIONS GMBH
    Inventors: Dominik Strasser, Jörg Grosse, Jan Lanik, Raik Brinkmann
  • SYSTEM AND METHOD FOR FORMAL FAULT PROPAGATION ANALYSIS
    Publication number: 20200200820
    Abstract: A system and method for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.
    Type: Application
    Filed: June 19, 2018
    Publication date: June 25, 2020
    Inventors: Dominik Strasser, Jörg Grosse, Jan Lanik, Raik Brinkmann