Abstract: A method for transmitting a bit sequence to be transmitted at a frequency fb. A set of codes is determined in advance, wherein each code is associated with a possible value from a block of Nb bits, and each code includes an ordered set of Ns binary symbols intended to be transmitted at a frequency fs. The method includes splitting the bit sequence into N blocks of Nb bits, the frequency fs and the numbers N and Nb being selected such that Ns×fb=N×Nb×fs, associating a code with each of the N blocks according to the value from the blocks, interleaving the binary symbols of the N codes respectively corresponding to the N blocks of bits to be transmitted, the interleaved binary symbols being transmitted at a frequency fc such that N×fs=fc.

Abstract: An emitting method, by an emitting device to at least one receiving station, of UWB messages, the emitting device including a simplex communication module for the emitting of UWB messages, a module for receiving wireless electrical energy suitable for receiving emitted electrical energy and for storing the electrical energy received in an electric accumulator, the method including a charging of the electric accumulator by the module for receiving wireless electrical energy, an evaluation of a criterion of sufficient electrical energy for the emitting of a UWB message, when the criterion of sufficient electrical energy for the emitting of a UWB message is satisfied, a selecting of a random emission delay and an emitting of the UWB message, by the simplex communication module, after the expiration of the random emission delay selected.

Abstract: A method for transmitting a bit sequence to be transmitted at a frequency fb. A set of codes is determined in advance, wherein each code is associated with a possible value from a block of Nb bits, and each code includes an ordered set of Ns binary symbols intended to be transmitted at a frequency fs. The method includes splitting the bit sequence into N blocks of Nb bits, the frequency fs and the numbers N and Nb being selected such that Ns×fb=N×Nb×fs, associating a code with each of the N blocks according to the value from the blocks, interleaving the binary symbols of the N codes respectively corresponding to the N blocks of bits to be transmitted, the interleaved binary symbols being transmitted at a frequency fc such that N×fs=fc.

Abstract: A radio-frequency energy harvesting circuit includes an antenna suitable for receiving the radio-frequency energy, a converter suitable for converting the radio-frequency energy received into a direct current electrical voltage, the “RF/DC converter”, an electrical energy storage capacity and an interface circuit arranged between an output port of the RF/DC converter and the electrical energy storage capacity. The interface circuit is a passive electrical circuit including a resistive load placed in series between the output port of the RF/DC converter and the electrical energy storage capacity, the resistive load being of static value equal to or greater than 400 kilo-ohms.

Abstract: A radio-frequency energy harvesting circuit includes an antenna suitable for receiving the radio-frequency energy, a converter suitable for converting the radio-frequency energy received into a direct current electrical voltage, the “RF/DC converter”, an electrical energy storage capacity and an interface circuit arranged between an output port of the RF/DC converter and the electrical energy storage capacity. The interface circuit is a passive electrical circuit including a resistive load placed in series between the output port of the RF/DC converter and the electrical energy storage capacity, the resistive load being of static value equal to or greater than 400 kilo-ohms.

Abstract: An emitting method, by an emitting device to at least one receiving station, of UWB messages, the emitting device including a simplex communication module for the emitting of UWB messages, a module for receiving wireless electrical energy suitable for receiving emitted electrical energy and for storing the electrical energy received in an electric accumulator, the method including a charging of the electric accumulator by the module for receiving wireless electrical energy, an evaluation of a criterion of sufficient electrical energy for the emitting of a UWB message, when the criterion of sufficient electrical energy for the emitting of a UWB message is satisfied, a selecting of a random emission delay and an emitting of the UWB message, by the simplex communication module, after the expiration of the random emission delay selected.

Abstract: A method for the detection of a pulse of a signal received by a receiver device, the received signal corresponding to data emitted with a predetermined period Tc, each piece of data being encoded by a presence or an absence of a pulse. The method includes: temporally offsetting of the received signal according to a predetermined number Ns of delays corresponding to different multiples of Tc, so as to generate Ns delayed signals; correlating, at a time that is a candidate for the detection of a pulse, the received signal with each of the delayed signals, in so as to obtain Ns correlation values associated with the candidate time; calculating a maximum correlation value among the Ns correlation values associated with the candidate time; and detecting a pulse of the received signal according to the maximum correlation value.

Abstract: A method for the detection of a pulse of a signal received by a receiver device, the received signal corresponding to data emitted with a predetermined period Tc, each piece of data being encoded by a presence or an absence of a pulse. The method includes: temporally offsetting of the received signal according to a predetermined number Ns of delays corresponding to different multiples of Tc, so as to generate Ns delayed signals; correlating, at a time that is a candidate for the detection of a pulse, the received signal with each of the delayed signals, in so as to obtain Ns correlation values associated with the candidate time; calculating a maximum correlation value among the Ns correlation values associated with the candidate time; and detecting a pulse of the received signal according to the maximum correlation value.

Abstract: A method for constructing orthogonal codes of length N for use in a network utilizing quasi-synchronous code division multiple access combined with time division duplexing. The method determines the balanced vectors of length N, being all possible cross-correlation vectors resulting from zero cross-correlation of codes of length N. An arbitrary code of length N is utilized, and a bitwise XOR-ing is performed with all the balanced vectors to produce a set of codes with which the arbitrary code is orthogonal. A bitwise XOR-ing of the original balanced vectors is performed and the code is added to a set of orthogonal codes if the result of the bitwise XOR-ing of the original balanced vectors is balanced. The method is repeated until the set of orthogonal codes is complete.

Abstract: A device for transferring data arrays between at least two buses, the device comprising storage means for storing at least one data array, a first input/output interface for transferring data arrays in a first direction from a first of the buses (RBUS) to the storage means and in a second direction from the storage means to the first bus (RBUS), a second input/output interface for transferring data arrays in a third direction from a second of the buses (MBUS) to the storage means and in a fourth direction from the storage means to the second bus (MBUS), the first and second interfaces being concurrently operable in each clock cycle, the device comprising means for receiving an instruction word within a clock cycle, the first interface being provided with first selecting means for selecting one of said first and second directions and the second interface being provided with second selecting means for selecting one of said third and fourth directions, the first and second selecting means being connected to said

Abstract: A method for constructing orthogonal codes of length N for use in a network utilizing quasi-synchronous code division multiple access combined with time division duplexing. The method determines the balanced vectors of length N, being all possible cross-correlation vectors resulting from zero cross-correlation of codes of length N. An arbitrary code of length N is utilized, and a bitwise XOR-ing is performed with all the balanced vectors to produce a set of codes with which the arbitrary code is orthogonal. A bitwise XOR-ing of the original balanced vectors is performed and the code is added to a set of orthogonal codes if the result of the bitwise XOR-ing of the original balanced vectors is balanced. The method is repeated until the set of orthogonal codes is complete.

Abstract: A method and system for constructing orthogonal codes of length N for use in a network utilizing quasi-synchronous code division multiple access combined with time division duplexing. The method determines the balanced vectors of length N, being all possible cross-correlation vectors resulting from zero cross-correlation of codes of length N. An arbitrary code of length N is utilized, and a bitwise XOR-ing is performed with all the balanced vectors to produce a set of codes with which the arbitrary code is orthogonal. A bitwise XOR-ing of the original balanced vectors is performed and the code is added to a set of orthogonal codes if the result of the bitwise XOR-ing of the original balanced vectors is balanced. The method is repeated until the set of orthogonal codes is complete.

Abstract: A device for transferring data arrays between at least two buses, the device comprising storage means for storing at least one data array, a first input/output interface for transferring data arrays in a first direction from a first of the buses (RBUS) to the storage means and in a second direction from the storage means to the first bus (RBUS), a second input/output interface for transferring data arrays in a third direction from a second of the buses (MBUS) to the storage means and in a fourth direction from the storage means to the second bus (MBUS), the first and second interfaces being concurrently operable in each clock cycle, the device comprising means for receiving an instruction word within a clock cycle, the first interface being provided with first selecting means for selecting one of said first and second directions and the second interface being provided with second selecting means for selecting one of said third and fourth directions, the first and second selecting means being connected to said

Abstract: A method and system for constructing orthogonal codes of length N for use in a network utilizing quasi-synchronous code division multiple access combined with time division duplexing. The method determines the balanced vectors of length N, being all possible cross-correlation vectors resulting from zero cross-correlation of codes of length N. An arbitrary code of length N is utilized, and a bitwise XOR-ing is performed with all the balanced vectors to produce a set of codes with which the arbitrary code is orthogonal. A bitwise XOR-ing of the original balanced vectors is performed and the code is added to a set of orthogonal codes if the result of the bitwise XOR-ing of the original balanced vectors is balanced. The method is repeated until the set of orthogonal codes is complete.

Abstract: A method of generating a waveform with a plurality of orthogonal PN codes for use in a communications network utilizing quasi-synchronous code division multiple access. The orthogonal PN codes modulate multiple data streams together with a non-orthogonal PN code having desirable auto-correlation properties. The result is a complex signal with time-aligned PN codes.

Abstract: A method for frame synchronization including the detection of an n-bit pattern with predetermined characteristics in a bitstream is described. The subject method includes the steps of extracting a first set of m bits, with m being smaller than or equal to n, from a first position in said bitstream, deriving from said first set an address of a location in a first memory, deriving from the contents of said location in said first memory at least one second position in said bitstream and at least one second set of bits to be extracted therefrom until said n-bit pattern is detected in said bitstream. An apparatus for performing the subject method is additionally described.