Patents by Inventor Jan Pawlak
Jan Pawlak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8900891Abstract: A method for manufacturing interdigitated back contact photovoltaic cells is disclosed. In one aspect, the method includes providing on a rear surface of a substrate a first doped layer of a first dopant type, and providing a dielectric masking layer overlaying it. Grooves are formed through the dielectric masking layer and first doped layer, extending into the substrate in a direction substantially orthogonal to the rear surface and extending in a lateral direction underneath the first doped layer at sides of the grooves. Directional doping is performed in a direction substantially orthogonal to the rear surface, thereby providing doped regions with dopants of a second dopant type at a bottom of the grooves. Dopant diffusion is performed to form at the rear side of the substrate one of the emitter regions and back surface field regions between the grooves and the other at the bottom of the grooves.Type: GrantFiled: June 14, 2011Date of Patent: December 2, 2014Assignee: IMECInventors: Bartlomiej Jan Pawlak, Tom Janssens
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Publication number: 20140217467Abstract: Obtaining a structure comprised of first and second layers of a first semiconductor materials and a strain relief buffer (SRB) layer between the first and second layers, forming a sidewall spacer on the sidewalls of an opening in the second layer, and forming a third semiconductor material in the opening, wherein the first, second and third semiconductor materials are different. A device includes first and second layers of first and second semiconductor materials and an SRB layer positioned above the first layer. The second layer is positioned above a first portion of the SRB layer, a region of a third semiconductor material is in an opening in the second layer and above a second portion of the SRB layer, and an insulating material is positioned between the region comprised of the third semiconductor material and the second layer.Type: ApplicationFiled: February 4, 2013Publication date: August 7, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Bartlomiej Jan Pawlak, Steven Bentley, Ajey Jacob
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Publication number: 20140174526Abstract: The disclosed technology generally relates to photovoltaic devices and methods of fabricating photovoltaic devices, and more particularly relates to interdigitated back contact photovoltaic cells and methods of fabricating the same. In one aspect, a method of forming first and second interdigitated electrodes on a semiconductor substrate comprises providing a dielectric layer on the rear surface of the semiconductor substrate. The method additionally comprises providing a metal seed layer on the dielectric layer. The method additionally comprises patterning the metal seed layer by laser ablation, thereby separating it into a first seed layer and a second seed layer with a separation region interposed therebetween, wherein the first seed layer and the second seed layer are interdigitated and electrically isolated from each other. The method further comprises thickening the first seed layer and the second seed layer by plating, thereby forming the first electrode and the second electrode.Type: ApplicationFiled: February 4, 2014Publication date: June 26, 2014Applicant: IMECInventors: Bartlomiej Jan Pawlak, Bartlomiej Sojka
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Patent number: 8716156Abstract: One illustrative method disclosed herein includes forming a mandrel structure above a semiconductor substrate, performing an oxidation process to oxidize at least a portion of the mandrel structure so as to thereby define oxidized regions on the mandrel structure, removing the oxidized regions to thereby defined a reduced thickness mandrel structure, forming a plurality of fins on the reduced thickness mandrel structure and performing an etching process to selectively remove at least a portion of the reduced thickness mandrel structure so as to thereby expose at least a portion of each of the fins.Type: GrantFiled: February 1, 2013Date of Patent: May 6, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Bartlomiej Jan Pawlak, Steven Bentley, Ajey Jacob
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Patent number: 8357569Abstract: The present disclosure provides a FinFET device and method of fabricating a FinFET device. The method includes providing a substrate, forming a fin structure on the substrate, forming a gate structure including a gate dielectric and gate electrode, the gate structure overlying a portion of the fin structure, forming a protection layer over another portion of the fin structure, and thereafter performing an implantation process to form source and drain regions.Type: GrantFiled: September 29, 2009Date of Patent: January 22, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Bartlomiej Jan Pawlak
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Patent number: 8187959Abstract: Method of producing a semiconductor device, comprising: a) providing a semiconductor substrate, b) making a first amorphous layer in a top layer of the semiconductor substrate by a suitable implant, the first amorphous layer having a first depth, c) implanting a first dopant into the semiconductor substrate to provide the first amorphous layer with a first doping profile, d) applying a first solid phase epitaxial regrowth action to partially regrow the first amorphous layer and form a second amorphous layer having a second depth that is less than the first depth and activate the first dopant, e) implanting a second dopant into the semiconductor substrate to provide the second amorphous layer with a second doping profile with a higher doping concentration than the first doping profile, f) applying a second solid phase epitaxial regrowth action to regrow the second amorphous layer and activate the second dopant.Type: GrantFiled: December 2, 2004Date of Patent: May 29, 2012Assignee: IMECInventors: Bartlomiej Jan Pawlak, Raymond James Duffy, Richard Lindsay
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Publication number: 20110303280Abstract: A method for manufacturing interdigitated back contact photovoltaic cells is disclosed. In one aspect, the method includes providing on a rear surface of a substrate a first doped layer of a first dopant type, and providing a dielectric masking layer overlaying it. Grooves are formed through the dielectric masking layer and first doped layer, extending into the substrate in a direction substantially orthogonal to the rear surface and extending in a lateral direction underneath the first doped layer at sides of the grooves. Directional doping is performed in a direction substantially orthogonal to the rear surface, thereby providing doped regions with dopants of a second dopant type at a bottom of the grooves. Dopant diffusion is performed to form at the rear side of the substrate one of the emitter regions and back surface field regions between the grooves and the other at the bottom of the grooves.Type: ApplicationFiled: June 14, 2011Publication date: December 15, 2011Applicant: IMECInventors: Bartlomiej Jan Pawlak, Tom Janssens
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Publication number: 20110073919Abstract: The present disclosure provides a FinFET device and method of fabricating a FinFET device. The method includes providing a substrate, forming a fin structure on the substrate, forming a gate structure including a gate dielectric and gate electrode, the gate structure overlying a portion of the fin structure, forming a protection layer over another portion of the fin structure, and thereafter performing an implantation process to form source and drain regions.Type: ApplicationFiled: September 29, 2009Publication date: March 31, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Bartlomiej Jan Pawlak
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Patent number: 7615430Abstract: The invention relates to a method of manufacturing a field effect transistor, in which a semiconductor body of silicon is provided at a surface thereof with a source region and a drain region of a first conductivity type, which regions are both provided with extensions, and with a gate region situated above the channel region. A pn-junction is formed between the extensions and a neighboring part of the channel region using an amorphizing implantation followed by two implantations of dopants of opposite conductivity type, before the gate region is formed and at an angle with the surface of the semiconductor body which is substantially equal to 90 degrees. A steep and abrupt vertical part of the pn-junction is thus formed with a very low leakage current due to the absence of implantations defects. In some embodiments, a low temperature anneal is used to regrow crystalline silicon.Type: GrantFiled: March 8, 2005Date of Patent: November 10, 2009Assignee: NXP B.V.Inventor: Bartlomiej Jan Pawlak
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Patent number: 7582547Abstract: Devices and methods for junction formation in manufacturing a semiconductor device are disclosed. The devices have shallow junction depths far removed from end-of range defects. The method comprises forming an amorphous region in a crystalline semiconductor such as silicon down to a first depth, followed by implantation of a substitutional element such as carbon to a smaller depth than the first depth. The region is then doped with suitable dopants, e.g. phosphorus or boron, and the amorphous layer recrystallized by a thermal process.Type: GrantFiled: August 3, 2007Date of Patent: September 1, 2009Assignees: Interuniversitair Microelektronica Centrum vzw (IMEC), Koninklijke Philips ElectronicsInventor: Bartlomiej Jan Pawlak
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Publication number: 20090140242Abstract: Method of producing a semiconductor device, comprising: a) providing a semiconductor substrate, b) making a first amorphous layer in a top layer of the semiconductor substrate by a suitable implant, the first amorphous layer having a first depth, c) implanting a first dopant into the semiconductor substrate to provide the first amorphous layer with a first doping profile, d) applying a first solid phase epitaxial regrowth action to partially regrow the first amorphous layer and form a second amorphous layer having a second depth that is less than the first depth and activate the first dopant, e) implanting a second dopant into the semiconductor substrate to provide the second amorphous layer with a second doping profile with a higher doping concentration than the first doping profile, f) applying a second solid phase epitaxial regrowth action to regrow the second amorphous layer and activate the second dopant.Type: ApplicationFiled: December 2, 2004Publication date: June 4, 2009Applicant: KONINKLIJKE PHILIPS ELECTRONIC, N.V.Inventors: Bartlomiej Jan Pawlak, Raymond James Duffy, Richard Lindsay
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Patent number: 7491616Abstract: The invention relates to a method of manufacturing a semiconductor device (10) in which a semiconductor body (1) of silicon is provided, at a surface thereof, with a semiconductor region (4) of a first conductivity type, in which region a second semiconductor region (2A, 3A) of a second conductivity type, opposite to the first conductivity type, is formed forming a pn-junction with the first semiconductor region (4) by the introduction of dopant atoms of the second conductivity type into the semiconductor body (1), and wherein, before the introduction of said dopant atoms, an amorphous region is formed in the semiconductor body (1) by means of an amorphizing implantation of inert atoms, and wherein, after the amorphizing implantation, temporary dopant atoms are implanted in the semiconductor body (1), and wherein, after introduction of the dopant atoms of the second conductivity type, the semiconductor body is annealed by subjecting it to a heat treatment at a temperature in the range of about 500 to about 80Type: GrantFiled: March 7, 2005Date of Patent: February 17, 2009Assignee: NXP B.V.Inventor: Bartlomiej Jan Pawlak
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Patent number: 7348229Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a field effect transistor, in which method a semiconductor body (1) of silicon is provided at a surface thereof with a source region (2) and a drain region (3) of a first conductivity type, which both are provided with extensions (2A,3A) and with a channel region (4) of a second conductivity type, opposite to the first conductivity type, between the source region (2) and the drain region (3) and with a gate region (5) separated from the surface of the semiconductor body (1) by a gate dielectric (6) above the channel region (4), and wherein a pocket region (7) of the second conductivity type and with a doping concentration higher than the doping concentration of the channel region (4) is formed below the extensions (2A,3A), and wherein the pocket region (7) is formed by implanting heavy ions in the semiconductor body (1), after which implantation a first annealing process is done at a moderate temperature and a second annealingType: GrantFiled: November 29, 2004Date of Patent: March 25, 2008Assignee: NXP B.V.Inventors: Bartlomiej Jan Pawlak, Raymond James Duffy
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Patent number: 7326620Abstract: A method of manufacturing a semiconductor device comprising a dual gate field effect transistor is disclosed, in which method a semiconductor body with a surface and of silicon is provided with a source region and a drain region of a first conductivity type and with a channel region of a second conductivity type, opposite to the first conductivity type, between the source region and the drain region and with a first gate region separated from the channel region by a first gate dielectric and situated on one side of the channel region and with a second gate region separated from the channel region by a second gate dielectric and situated on an opposite side of the channel region, and wherein both gate regions are formed within a trench formed in the semiconductor body.Type: GrantFiled: March 11, 2005Date of Patent: February 5, 2008Assignees: Interuniversitair Microelektronica Centrum (IMEC), Koninklijke Philips ElectronicsInventor: Bartlomiej Jan Pawlak
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Patent number: 7122452Abstract: A method of producing a semiconductor device on a silicon on insulator (SOI) substrate is disclosed. In one aspect, the method comprises providing a device with a monocrystalline semiconductor layer on an insulating layer; providing a mask on the semiconductor layer to provide first shielded portions and first unshielded portions, amorphizing the first unshielded portions to yield first amorphized portions of the monocrystalline semiconductor layer, implanting a first dopant in the first amorphized portions, applying a first solid phase epitaxial regrowth action to the semiconductor device while using the first shielded portions as monocrystalline seeds.Type: GrantFiled: March 15, 2005Date of Patent: October 17, 2006Assignees: Interuniversitair Microelektronica Centrum (IMEC) vzw, Koninklijke Philips ElectronicsInventor: Bartlomiej Jan Pawlak
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Publication number: 20060078986Abstract: The present invention provides analytical devices comprising primary and secondary flow paths. A secondary flow path is configured to allow for a portion of a liquid sample to enter the secondary flow path from a primary flow path and subsequently be drawn back into the primary flow path, thereby providing sequential delivery of a portion of the sample to downstream locations.Type: ApplicationFiled: September 30, 2005Publication date: April 13, 2006Applicant: Quidel CorporationInventors: Peter Ly, Rajesh Mehra, Catherine Pawlak, Romy Meris, Jan Pawlak
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Publication number: 20060029926Abstract: Compositions and processes for qualitative or quantitative one-step, two-site, tag/anti-tag or competitive non-bibulous lateral flow (immunochromatographic) assays for analytes in body fluids including chemically modified proteins as blocking and/or dispersing agents in conjunction with additives eliminating non-specific interference with the detection agents and/or binding partner caused by endogenous polypeptide constituents. Composition of the chemically modified proteins can be albumins. Composition of the chemically modified albumins can have altered charge and/or molecular weight. Process for composition of the chemically modified proteins can be prepared by modification of the nucleophilic groups. The chemical modification of nucleophilic groups in albmins can be introduced by anhydrides, alkyl acetimidates, methylating and/or cross-linking agents. The additives eliminating non-specific interference can be chemically modified albumins, heterophilic blockers and chaotropic agents.Type: ApplicationFiled: March 9, 2005Publication date: February 9, 2006Applicant: METRIKA, Inc.Inventors: Jan Pawlak, John Bartz, Catherine Pawlak, Patrick Sexton, Charles Zahl, Tilden Capen-Frederick, Victor Manneh
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Patent number: 5804452Abstract: The present invention provides devices and methods for the detection of creatinine in biological fluids using lateral flow methodologies. The invention is particularly useful in providing one step creatinine assays for correcting urinary steroid hormone assays.Type: GrantFiled: April 27, 1995Date of Patent: September 8, 1998Assignee: Quidel CorporationInventors: Alan Pronovost, Jan Pawlak
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Patent number: 4195172Abstract: The new compounds, N-methylglucamine salts of N-glycosyl derivatives of polyene macrolides particularly N-methylglucamine salts of N-glycosyl derivatives of amphotericin B, polifungin and nystatin are described herein. These compounds exhibit high pharamacological activity in some topical and sistemic fungal infections. The product is prepared by reaction of an amino group containing polyene macrolide with an aldose or ketose mono- or oligosaccharide, in an organic solvent medium or in the mixture of solvents characterized in that the formed N-glycosyl derivatives is precipitated from the reaction medium by water or with an aqueous solution of inorganic salt, preferably ammonium sulphate, and after crystallization from a higher alkanol of C.sub.3-6 atoms, preferably n-butanol transformed into a salt, preferably an N-methylglucamine salt and then crystallized from higher alkanol, preferably n-butanol.Type: GrantFiled: May 10, 1978Date of Patent: March 25, 1980Assignees: Politechnika Gdanska, Instytut Przemyslu FarmaceutycznegoInventors: Leonard Falkowski, Zuzanna Kowszyk-Gindifer, Zofia Plociennik, Jan Zielinski, Halina Dahlig, Jerzy Golik, Ewa Jakobs, Pawel Kolodziejczyk, Elzbieta Bylec, Danuta Roslik-Kaminska, Wladyslawa Wagner, Jan Pawlak, Edward Borowski
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Patent number: 4093796Abstract: A new class of polyene macrolide antibiotics which exhibit valuable therapeutic properties are obtained by reaction of said antibiotics containing at least one amino group with mono- or oligosaccharides, and/or their derivatives in a suitable solvent.A series of such have been obtained and examined. They all exhibit a high biological activity and form salts which are soluble in water.Said sugar derivatives of antibiotics can be used as antifungal agents, also as substances to reduce the overgrowth of the prostrate gland and cholesterol level in the blood.Type: GrantFiled: August 10, 1972Date of Patent: June 6, 1978Assignee: Politechnika GdanskaInventors: Leonard Falkowski, Miroslaw Bobrowski, Helena Buluk, Elzbieta Bylec, Barbara Cybulska, Jerzy Golik, Pawel Kolodziejczyk, Jan Pawlak, Andrzej Rudowski, Jan Zielinski, Tadeusz Ziminski, Edward Borowski