Abstract: In one form, a switching controller includes a buck controller and a bypass circuit. The buck controller has an input for receiving a variable voltage, an output for providing a buck voltage by switching the variable voltage into an inductive output filter according to a switching signal having a variable duty cycle to regulate a current into a load. The bypass circuit is coupled to the buck controller for comparing the variable duty cycle of the switching signal to a threshold, for activating a bypass signal in response to the variable duty cycle exceeding the threshold, and for subsequently de-activating the bypass signal according to a predetermined algorithm.

Abstract: In one form, a switching controller includes a buck controller and a bypass circuit. The buck controller has an input for receiving a variable voltage, an output for providing a buck voltage by switching the variable voltage into an inductive output filter according to a switching signal having a variable duty cycle to regulate a current into a load. The bypass circuit is coupled to the buck controller for comparing the variable duty cycle of the switching signal to a threshold, for activating a bypass signal in response to the variable duty cycle exceeding the threshold, and for subsequently de-activating the bypass signal according to a predetermined algorithm.

Abstract: Capacitive coupling may enable more tightly synchronized operation of components in a multi-domain distributed driver that provides slope-controlled switching of differential signal lines. One illustrative distributed driver includes: a first set of transistors each coupled to drive a first bus line; a first set of delay elements configured to enable and disable the first set of transistors sequentially; a second set of transistors each coupled to drive a second bus line; a second set of delay elements configured to enable and disable the second set of transistors sequentially; and at least one capacitance coupling a first node in the first set of delay elements to a corresponding second node in the second set of delay elements to synchronize signal transitions at the first and second nodes.

Abstract: Circuits and processes for locking a voltage-controlled oscillator (VCO) at a high frequency signal are described. A circuit may include a voltage-controlled oscillator configured to generate a high frequency signal based on a control signal, a dummy load parallel to the voltage-controlled oscillator and configured to receive the control signal via a switch, and a digital-to-analog converter coupled to the voltage-controlled oscillator where the control signal is generated based on an output of the digital-to-analog converter.

Abstract: Circuits and processes for locking a voltage-controlled oscillator (VCO) at a high frequency signal are described. A circuit may include an adjustable current converter (ACC), coupled at an input terminal to a power source, operable to output a control signal (VC) at an output terminal. A first switch may be coupled to the ACC and to the VCO. The VCO, when in an “ON” state, receives the control signal and outputs a high frequency signal (VHF). A digital filter may be coupled to the VCO and operable to receive the VHF. Based on the VHF, the digital filter generates a data signal having a data value. The circuit may also include a digital-to-analog converter (DAC) operable to receive the data signal and, based on the data value, output an adjustment signal to the ACC. The ACC may adjust the control signal based on the adjustment signal received from the DAC.

Abstract: Capacitive coupling may enable more tightly synchronized operation of components in a multi-domain distributed driver that provides slope-controlled switching of differential signal lines. One illustrative distributed driver includes: a first set of transistors each coupled to drive a first bus line; a first set of delay elements configured to enable and disable the first set of transistors sequentially; a second set of transistors each coupled to drive a second bus line; a second set of delay elements configured to enable and disable the second set of transistors sequentially; and at least one capacitance coupling a first node in the first set of delay elements to a corresponding second node in the second set of delay elements to synchronize signal transitions at the first and second nodes.

Abstract: Devices, systems, and methods for locking a voltage controlled oscillator (VCO) at a high frequency may include use of a VCO and an integrator, which generates and outputs a control signal to the VCO, based on an inverting signal and a reference signal. The control signal locks the VCO to a high frequency signal (FH). A frequency divider is coupled to the VCO, receives FH from the VCO, divides FH by a factor “F”, and outputs a low frequency signal (FL). A switched capacitor resistor circuit (SCRC) is coupled to the frequency divider and the integrator. The SCRC receives FL from the frequency divider and generates the inverting signal. An integrating capacitor is coupled across an inverting and an output terminal of op-amp in the integrator. The output of the op-amp provides an integrator signal, which may be (optionally) filtered to produce the control signal.

Abstract: Operating DC to DC power converters. At least some of the example embodiments are methods including: driving current through an inductance in a first on cycle of the power converter; comparing, by a comparator, a signal indicative of current through the inductance coupled to a first input of the comparator to a threshold applied to a second input of the comparator, and asserting a comparator output responsive to the signal indicative of current meeting the threshold; sampling a differential voltage across the first and second inputs, the sampling responsive to assertion of a comparator output, and the differential voltage indicative of propagation delay through the comparator; and compensating the comparator in a second on cycle for the compensation delay based on the differential voltage, the second on cycle subsequent to the first on cycle.

Abstract: According to an aspect, a controller includes an error circuit configured to receive a clamping voltage and a feedback signal, the error circuit configured to generate a regulation reference signal based on the clamping voltage and the feedback signal, a PWM circuit configured to receive the regulation reference signal and a current sense signal, the PWM circuit configured to generate a limit signal or a regulation signal based on the regulation reference signal and the current sense signal, a clamp circuit configured to increase a magnitude of the clamping voltage in response to the regulation signal being an active state and decrease the magnitude of the clamping voltage in response to the limit signal being the active state, and a drive circuit configured to generate a drive signal for regulating the output current in response to at least one of the limit signal or the regulation signal.

Abstract: Devices, systems, and methods for locking a voltage controlled oscillator (VCO) at a high frequency may include use of a VCO and an integrator, which generates and outputs a control signal to the VCO, based on an inverting signal and a reference signal. The control signal locks the VCO to a high frequency signal (FH). A frequency divider is coupled to the VCO, receives FH from the VCO, divides FH by a factor “F”, and outputs a low frequency signal (FL). A switched capacitor resistor circuit (SCRC) is coupled to the frequency divider and the integrator. The SCRC receives FL from the frequency divider and generates the inverting signal. An integrating capacitor is coupled across an inverting and an output terminal of op-amp in the integrator. The output of the op-amp provides an integrator signal, which may be (optionally) filtered to produce the control signal.

Abstract: Circuits and processes for locking a voltage-controlled oscillator (VCO) at a high frequency signal are described. A circuit may include an adjustable current converter (ACC), coupled at an input terminal to a power source, operable to output a control signal (VC) at an output terminal. A first switch may be coupled to the ACC and to the VCO. The VCO, when in an “ON” state, receives the control signal and outputs a high frequency signal (VHF). A digital filter may be coupled to the VCO and operable to receive the VHF. Based on the VHF, the digital filter generates a data signal having a data value. The circuit may also include a digital-to-analog converter (DAC) operable to receive the data signal and, based on the data value, output an adjustment signal to the ACC. The ACC may adjust the control signal based on the adjustment signal received from the DAC.

Abstract: Operating DC to DC power converters. At least some of the example embodiments are methods including: driving current through an inductance in a first on cycle of the power converter; comparing, by a comparator, a signal indicative of current through the inductance coupled to a first input of the comparator to a threshold applied to a second input of the comparator, and asserting a comparator output responsive to the signal indicative of current meeting the threshold; sampling a differential voltage across the first and second inputs, the sampling responsive to assertion of a comparator output, and the differential voltage indicative of propagation delay through the comparator; and compensating the comparator in a second on cycle for the compensation delay based on the differential voltage, the second on cycle subsequent to the first on cycle.

Abstract: Detecting failure modes of DC to DC power converters. In a system comprising a lighting microcontroller communicatively coupled to a direct current (DC) to DC power converter coupled to light-emitting diodes (LEDs) by way of an inductor, an example method may include: commanding, by the lighting microcontroller, the power converter to control an average current provided to the LEDs; reading, by the lighting microcontroller, values from the power converter; and detecting, by the lighting controller, one or more failure modes of the power converter based on the values.

Abstract: Various embodiments of apparatuses, systems and methods for regulating the currents provided by a DCDC buck converters to an LED unit are provided. In accordance with at least one embodiment, a regulating element operable to instruct and regulate the periods during which a first switch of a driver module, used to control the operation of a buck converter module, is configured into at least one of a first operating state and a second operating state such that the maximum and minimum currents provided by the buck converter module to a load, such as an LED unit, over a given duty cycle are symmetrically disposed about an average current provided to the LED unit during the duty cycle, where the average current provided is substantially equal to a target current for the LED unit.

Abstract: Various embodiments of apparatuses, systems and methods for regulating the currents provided by a DCDC buck converters to an LED unit are provided. In accordance with at least one embodiment, a device includes a time-off module configured to output a time-off signal when an output voltage of a power supply reaches a predetermined threshold; a timer module configured to determine a first duration, and after waiting a second duration, output a measured time signal; and a control module, coupled to each of the timer module and the time-off module, configured to output a set signal during a current cycle of the power supply, wherein the “on” slate for the current cycle occurs while the control module outputs the set signal and ends when the control module receives the measured time signal.

Abstract: Various embodiments of apparatuses, systems and methods for regulating the currents provided by a DCDC buck converters to an LED unit are provided. In accordance with at least one embodiment, a device includes a time-off module configured to output a time-off signal when an output voltage of a power supply reaches a predetermined threshold; a timer module configured to determine a first duration, and after waiting a second duration, output a measured time signal; and a control module, coupled to each of the timer module and the time-off module, configured to output a set signal during a current cycle of the power supply, wherein the “on” slate for the current cycle occurs while the control module outputs the set signal and ends when the control module receives the measured time signal.

Abstract: Various embodiments of apparatuses, systems and methods for regulating the currents provided by a DCDC buck converters to an LED unit are provided. In accordance with at least one embodiment, a regulating element operable to instruct and regulate the periods during which a first switch of a driver module, used to control the operation of a buck converter module, is configured into at least one of a first operating state and a second operating state such that the maximum and minimum currents provided by the buck converter module to a load, such as an LED unit, over a given duty cycle are symmetrically disposed about an average current provided to the LED unit during the duty cycle, where the average current provided is substantially equal to a target current for the LED unit.

Abstract: Various embodiments of apparatuses, systems and methods for regulating the currents provided by a DCDC buck converters to an LED unit are provided. In accordance with at least one embodiment, a regulating module operable to instruct and regulate the periods during which a first switch of a driver module, used to control the operation of a buck converter module, is configured into at least one of the first operating state and the second operating state such that the maximum and minimum currents provided by the buck converter module to a load, such as an LED unit, over a given duty cycle are symmetrically disposed about an average current provided to the LED unit during the duty cycle, where the average current provided is substantially equal to a target current for the LED unit.

Abstract: In one form, a capacitor voltage limiter (240), comprises a supply node (244), a pass element (242) having a first current electrode coupled to the supply node (244), a control electrode, and a second current electrode. The second current electrode is adapted to be coupled to an external storage capacitor (250). Additionally, the capacitor voltage limiter includes an amplifier having a non-inverting input for receiving a reference voltage, and an inverting input coupled to the second current electrode of the pass element (242). The amplifier includes an output coupled to the control electrode of the pass element (242). The capacitor voltage limiter also includes a rectifier (241) having an input coupled to the second current electrode of the pass element (242), and an output coupled to the first current electrode of the pass element (242).

Abstract: A regulated mirror current source circuit has an output transistor, a regulator for controlling the output circuit, and a current mirror having two or more current paths. The first path of the mirror is coupled in series with a current path of the output circuit, and the second path is coupled to the regulator, to provide feedback. The feedback can provide better precision, or reduced component area. The circuit can include cascode transistors, and the regulator can have integral control. The output transistor gate-source voltage is overdriven to reduce “on” resistance of the output transistor. When the output transistor is a high voltage transistor, its area can be reduced without sacrificing compliance.