Patents by Inventor Jan Proschwitz
Jan Proschwitz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990408Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a redistribution layer (RDL) having a conductive layer in a first dielectric layer, and a second dielectric layer over the conductive and first dielectric layers. The RDL comprises an extended portion having a first thickness that vertically extends from a bottom surface of the first dielectric layer to a topmost surface of the second dielectric layer. The electronic package comprises a die on the RDL, where the die has sidewall surfaces, a top surface, and a bottom surface that is opposite from the top surface, and an active region on the bottom surface of the die. The first thickness is greater than a second thickness of the RDL that vertically extends from the bottom surface of the first dielectric layer to the bottom surface of the die. The extended portion is over and around the sidewall surfaces.Type: GrantFiled: March 27, 2020Date of Patent: May 21, 2024Assignee: Intel CorporationInventors: Thomas Wagner, Jan Proschwitz
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Patent number: 11804683Abstract: Embodiments are generally directed to a snap button fastener providing electrical connection. An embodiment of a fastener includes a first mechanical part, the first mechanical part including at least a stud portion, the first mechanical part including a first electrical connector; a second mechanical part, the second mechanical part including at least a socket portion with a spring element and the socket portion, the second mechanical part including a second electrical connector. The stud portion of the first mechanical part and the socket portion of second mechanical part, if separated, are to interlock upon the application of a first force towards each other, and, if interlocked, to separate upon the application of a second force away from each other.Type: GrantFiled: May 23, 2022Date of Patent: October 31, 2023Assignee: Intel CorporationInventors: Hans-Joachim Barth, Bastiaan Elshof, Jan Proschwitz
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Publication number: 20230317562Abstract: A die package comprises a semiconductor die comprising a first face, a second face on an opposing second side, an active layer located between the first face and the second face, a first electrical pathway between the first face and the active layer, a second electrical pathway between the second face and the active layer, a first contact pad coupled to the first face and electrically connected to the first electrical pathway, and a second contact pad coupled to the second face and electrically connected to the second electrical pathway. In an example, the first electrical pathway is configured to transmit one or more signals between the first contact pad and the active layer and the second electrical pathway is configured to transmit electrical power between the second contact pad and the active layer.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Inventors: Bernd Waidhas, Jan Proschwitz, Stefan Reif, Vishnu Prasad, Georg Seidemann
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Publication number: 20230317544Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. For example, in some embodiments, a microelectronic assembly may include a substrate having a first surface including a cavity and an opposing second surface; a die above the cavity and electrically coupled to the second surface of the substrate; a circuit board attached to the substrate; and a cooling apparatus at least partially nested in the cavity, wherein the cooling apparatus is in thermal contact with the die. In some embodiments, a microelectronic assembly may include a circuit board having a surface including a cavity; a substrate having a first surface attached to the circuit board and a die electrically coupled to an opposing second surface; and a cooling apparatus at least partially nested in the cavity, wherein the cooling apparatus is in thermal contact with the die.Type: ApplicationFiled: March 21, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Jan Proschwitz, Sonja Koller, Thomas Wagner, Vishnu Prasad, Wolfgang Molzer
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Publication number: 20230317681Abstract: Disclosed herein are microelectronic packages having thermally conductive layers and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies connected to the substrate and/or each other to form a die stack. The dies may have a perimeter. A thermally conductive layer may be located in between the respective dies. The thermally conductive layers may extend past at least a portion of the perimeters, thereby providing enhanced cooling of the die stack.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Sonja Koller, Vishnu Prasad, Bernd Waidhas, Eduardo De Mesa, Lizabeth Keser, Thomas Wagner, Mohan Prashanth Javare Gowda, Abdallah Bacha, Jan Proschwitz
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Publication number: 20230317551Abstract: Disclosed herein are microelectronics packages that include thermal pillars for at least localized extraction of generated heat and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies stacked on the substrate with at least one of the plurality of dies connected to the substrate. A heat spreader may be located proximate at least a portion of the plurality of dies. Respective thermal pillars from a plurality of thermal pillars may extend from at least one of the plurality dies to the heat spreader. Each of the plurality of thermal pillars may define a respective pathway from at least one of the plurality of dies to the heat spreader.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Inventors: Vishnu Prasad, Abdallah Bacha, Mohan Prashanth Javare Gowda, Lizabeth Keser, Thomas Wagner, Bernd Waidhas, Sonja Koller, Eduardo De Mesa, Jan Proschwitz
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Publication number: 20230307300Abstract: A semiconductor package comprises a package substrate comprised of comprised of layers of a first material. The semiconductor package includes an integrated circuit (IC) attached to the substrate at a first surface of the IC through a plurality of vias. The semiconductor package includes at least one interface layer comprised of an interface material different from the first material and sealed from exposure to air. The interface material can comprise a moisture-sensitive nonconductive material and can be disposed within the package substrate or between the first surface of the IC and the package substrate, among other locations. Other systems, apparatuses and methods are described.Type: ApplicationFiled: March 28, 2022Publication date: September 28, 2023Inventors: Jan Proschwitz, Stefan Reif, Bernd Waidhas, Vishnu Prasad
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Publication number: 20230299032Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a die having a first conductive contact on a surface; a substrate having a second conductive contact on a surface; and an interconnect electrically coupling the first conductive contact of the die and the second conductive contact of the substrate, wherein the interconnect includes a portion of a nanowire on the second conductive contact and an intermetallic compound (IMC) surrounding at least a portion of the nanowire on the second conductive contact.Type: ApplicationFiled: March 21, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: Bernd Waidhas, Jan Proschwitz, Stefan Reif, Vishnu Prasad
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Publication number: 20230299043Abstract: Embodiments of a microelectronic assembly comprises a first layer, a second layer and a third layer in a stack; a package substrate in the first layer, the package substrate comprising a metallic via structure; a first integrated circuit (IC) die surrounded by an organic dielectric material in the second layer, the first IC die coupled to the package substrate; a second IC die in the third layer, the second IC die coupled to the first IC die; and a third IC die in the third layer, the third IC die coupled to the first IC die. An electrically conductive pathway in the first IC die electrically couples the third IC die and the second IC die, and the first IC die is coupled to the package substrate with a thermally conductive material in contact with the metallic via structure in the package substrate.Type: ApplicationFiled: March 18, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: Bernd Waidhas, Sonja Koller, Jan Proschwitz, Eduardo De Mesa
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Publication number: 20230300975Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. For example, in some embodiments, a microelectronic assembly may include a substrate having a surface including a first cavity; a first die at least partially nested in the first cavity and electrically coupled to the substrate; and a circuit board having a surface including a second cavity, wherein the surface of the substrate is electrically coupled to the surface of the circuit board, and wherein the first die extends at least partially into the second cavity in the circuit board.Type: ApplicationFiled: March 21, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: Jan Proschwitz, Sonja Koller, Thomas Wagner, Vishnu Prasad, Wolfgang Molzer
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Publication number: 20230282546Abstract: Embodiments of a microelectronic assembly comprise an integrated circuit (IC) die and a package substrate having a core and redistribution layers on either side of the core. The IC die is coupled to a face of the package substrate, the face being parallel to the core. The core comprises one of glass, ceramic, and metal. The redistribution layers comprise one or more layers of a dielectric material, with conductive traces adjacent to the one or more layers of the dielectric material and conductive vias through the one or more layers of the dielectric material. The core comprises a hollow channel.Type: ApplicationFiled: March 3, 2022Publication date: September 7, 2023Applicant: Intel CorporationInventors: Bernd Waidhas, Sonja Koller, Jan Proschwitz, Eduardo De Mesa
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Publication number: 20230282615Abstract: A microelectronic assembly is provided, comprising: an interposer having a first side and a second side opposite to the first side; a plurality of integrated circuit (IC) dies in a plurality of layers on the first side of the interposer, the plurality of IC dies being encased by a dielectric material; a package substrate on the second side of the interposer; a plurality of conductive vias through the plurality of layers; and redistribution layers adjacent to the layers in the plurality of layers, at least some of the redistribution layers comprising conductive traces coupling the conductive vias to the IC dies.Type: ApplicationFiled: March 3, 2022Publication date: September 7, 2023Applicant: Intel CorporationInventors: Thomas Wagner, Abdallah Bacha, Vishnu Prasad, Mohan Prashanth Javare Gowda, Bernd Waidhas, Sonja Koller, Eduardo De Mesa, Jan Proschwitz, Lizabeth Keser
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Publication number: 20220285898Abstract: Embodiments are generally directed to a snap button fastener providing electrical connection. An embodiment of a fastener includes a first mechanical part, the first mechanical part including at least a stud portion, the first mechanical part including a first electrical connector; a second mechanical part, the second mechanical part including at least a socket portion with a spring element and the socket portion, the second mechanical part including a second electrical connector. The stud portion of the first mechanical part and the socket portion of second mechanical part, if separated, are to interlock upon the application of a first force towards each other, and, if interlocked, to separate upon the application of a second force away from each other.Type: ApplicationFiled: May 23, 2022Publication date: September 8, 2022Inventors: Hans-Joachim Barth, Bastiaan Elshof, Jan Proschwitz
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Patent number: 11342720Abstract: Embodiments are generally directed to a snap button fastener providing electrical connection. An embodiment of a fastener includes a first mechanical part, the first mechanical part including at least a stud portion, the first mechanical part including a first electrical connector; a second mechanical part, the second mechanical part including at least a socket portion with a spring element and the socket portion, the second mechanical part including a second electrical connector. The stud portion of the first mechanical part and the socket portion of second mechanical part, if separated, are to interlock upon the application of a first force towards each other, and, if interlocked, to separate upon the application of a second force away from each other.Type: GrantFiled: October 22, 2020Date of Patent: May 24, 2022Assignee: Intel CorporationInventors: Hans-Joachim Barth, Bastiaan Elshof, Jan Proschwitz
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Publication number: 20210305158Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a redistribution layer (RDL) having a conductive layer in a first dielectric layer, and a second dielectric layer over the conductive and first dielectric layers. The RDL comprises an extended portion having a first thickness that vertically extends from a bottom surface of the first dielectric layer to a topmost surface of the second dielectric layer. The electronic package comprises a die on the RDL, where the die has sidewall surfaces, a top surface, and a bottom surface that is opposite from the top surface, and an active region on the bottom surface of the die. The first thickness is greater than a second thickness of the RDL that vertically extends from the bottom surface of the first dielectric layer to the bottom surface of the die. The extended portion is over and around the sidewall surfaces.Type: ApplicationFiled: March 27, 2020Publication date: September 30, 2021Inventors: Thomas WAGNER, Jan PROSCHWITZ
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Publication number: 20210044065Abstract: Embodiments are generally directed to a snap button fastener providing electrical connection. An embodiment of a fastener includes a first mechanical part, the first mechanical part including at least a stud portion, the first mechanical part including a first electrical connector; a second mechanical part, the second mechanical part including at least a socket portion with a spring element and the socket portion, the second mechanical part including a second electrical connector. The stud portion of the first mechanical part and the socket portion of second mechanical part, if separated, are to interlock upon the application of a first force towards each other, and, if interlocked, to separate upon the application of a second force away from each other.Type: ApplicationFiled: October 22, 2020Publication date: February 11, 2021Inventors: Hans-Joachim Barth, Bastiaan Elshof, Jan Proschwitz
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Patent number: 10886680Abstract: Embodiments are generally directed to a snap button fastener providing electrical connection. An embodiment of a fastener includes a first mechanical part, the first mechanical part including at least a stud portion, the first mechanical part including a first electrical connector; a second mechanical part, the second mechanical part including at least a socket portion with a spring element and the socket portion, the second mechanical part including a second electrical connector. The stud portion of the first mechanical part and the socket portion of second mechanical part, if separated, are to interlock upon the application of a first force towards each other, and, if interlocked, to separate upon the application of a second force away from each other.Type: GrantFiled: January 28, 2019Date of Patent: January 5, 2021Assignee: Intel CorporationInventors: Hans-Joachim Barth, Bastiaan Elshof, Jan Proschwitz
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Publication number: 20190393659Abstract: Embodiments are generally directed to a snap button fastener providing electrical connection. An embodiment of a fastener includes a first mechanical part, the first mechanical part including at least a stud portion, the first mechanical part including a first electrical connector; a second mechanical part, the second mechanical part including at least a socket portion with a spring element and the socket portion, the second mechanical part including a second electrical connector. The stud portion of the first mechanical part and the socket portion of second mechanical part, if separated, are to interlock upon the application of a first force towards each other, and, if interlocked, to separate upon the application of a second force away from each other.Type: ApplicationFiled: January 28, 2019Publication date: December 26, 2019Inventors: Hans-Joachim Barth, Bastiaan Elshof, Jan Proschwitz
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Patent number: 10347558Abstract: Embodiments herein generally relate to the field of package assembly to facilitate thermal conductivity. A package may have a hanging die, and attach to a printed circuit board (PCB). The package may have an active side plane and an inactive side plane opposite the first active side plane. The package may also have a ball grid array (BGA) matrix having a height determined by a distance of a furthest point of the BGA matrix from the active side plane of the package. The package may have a hanging die attached to the active side plane of the package, the hanging die having a z-height greater than the BGA matrix height. When package is attached to the PCB, the hanging die may fit into an area on the PCB that is recessed or has been cut away, and a thermal conductive material may connect the hanging die and the PCB.Type: GrantFiled: August 31, 2015Date of Patent: July 9, 2019Assignee: INTEL IP CORPORATIONInventors: Christian Geissler, Georg Seidemann, Sonja Koller, Jan Proschwitz
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Patent number: 10193288Abstract: Embodiments are generally directed to a snap button fastener providing electrical connection. An embodiment of a fastener includes a first mechanical part, the first mechanical part including at least a stud portion, the first mechanical part including a first electrical connector; a second mechanical part, the second mechanical part including at least a socket portion with a spring element and the socket portion, the second mechanical part including a second electrical connector. The stud portion of the first mechanical part and the socket portion of second mechanical part, if separated, are to interlock upon the application of a first force towards each other, and, if interlocked, to separate upon the application of a second force away from each other.Type: GrantFiled: April 13, 2017Date of Patent: January 29, 2019Assignee: INTEL CORPORATIONInventors: Hans-Joachim Barth, Bastiaan Elshof, Jan Proschwitz