Abstract: Methods, computer program products, and/or systems are provided that perform the following operations: setting a memory buffer having contiguous memory blocks; obtaining a decision tree comprising nodes including split nodes and leaf nodes, wherein each of the split nodes includes at least two child nodes that are ordered according to a likelihood of accessing a child node after each of the split nodes; mapping the nodes onto respective blocks of the memory blocks, each of the memory blocks storing attributes of a corresponding one of the nodes, wherein each of the split nodes and any child nodes of each split node are mapped onto successive blocks, wherein ordered child nodes of a same one of the split nodes are mapped onto successive blocks; executing the nodes by processing the attributes of the nodes as accessed from the memory according to an order of the memory blocks in the memory buffer.

Abstract: A method of dynamically optimizing decision tree inference is provided. The method, which is performed at the computerized system, repeatedly executes one or more decision trees for inference purposes and repeatedly performs an optimization procedure according to two-phase cycles. Each cycle includes two alternating phases, i.e., a first phase followed by a second phase. The decision trees are executed based on a reference data structure, whereby attributes of nodes of the decision trees are repeatedly accessed from the reference data structure during the first phase of each of the cycles. First, the accessed attributes are monitored during the first phase of each cycle, which leads to update statistical characteristics of the nodes. Second, a substitute data structure is configured during the second phase of each cycle based on the updated statistical characteristics. Third, the reference data structure is updated in accordance with the substitute data structure.

Abstract: A tensor representation of a machine learning inferences to be performed is built by forming complementary tensor subsets that respectively correspond to complementary subsets of one or more leaf nodes of one or more decision trees based on statistics of the one or more leaf nodes of the one or more decision trees and data capturing attributes of one or more split nodes of the one or more decision trees and the one or more leaf nodes of the decision trees. The complementary tensor subsets are ranked such that a first tensor subset and a second tensor subset of the complementary tensor subsets correspond to a first leaf node subset and a second leaf node subset of the complementary subsets of the one or more leaf nodes.

Abstract: Accessing a value M identifying M top levels of one or more N decision trees, wherein 1 ? M < Min(L1, ...., LN) and wherein a M top levels defines top nodes for each of the N decision trees, and wherein for each decision tree Ti of the N decision trees. Identifying one or more subtrees subtended by respective subsets of remaining nodes of each decision tree Ti, a remaining nodes including all of the nodes of said each decision tree Ti but its top nodes. Processing each of the K input records through a top nodes of said each decision tree Ti to associate each of the K input records with a single, respective one of the subtrees of each decision tree Ti, wherein K × N associations are obtained in total for the N decision trees and the K input records.

Abstract: A method and computer program product for performing machine learning inferences are disclosed. A set of input records to be processed by decision trees is selected, and the decision trees are run. Running the decision trees includes identifying operations to be performed as matrix elements, wherein the matrix elements correspond to the input records. Running the decision trees also includes using vector processing to process disjoint subsets of the matrix elements based on vector instructions operating on data stored in vector registers, such that the matrix elements of each subset of the disjoint subsets are processed in parallel. All leaf nodes of each decision tree involved are processed as split nodes looping to themselves until a termination condition is met. The termination condition is met if at least one of the leaf nodes has been reached for each of the decision trees involved.

Abstract: A method is provided for accelerating machine learning inferences. The method uses an ensemble model run on input data. This ensemble model involves several base learners, where each of the base learners has been trained. The method first schedules tasks for execution. As a result of the task scheduling, one of the base learners is executed based on a subset of the input data. The execution of the tasks is then started to obtain respective task outcomes. An exit condition is repeatedly evaluated while executing the tasks by computing a deterministic function of the task outcomes obtained so far. This deterministic function output values indicate whether an inference result of the ensemble model has converged. Accordingly, the execution of the tasks can be interrupted if the exit condition evaluated last is found to be fulfilled. Eventually, an inference result of the ensemble model is estimated based on the task outcomes.

Abstract: Methods, computer program products, and/or systems are provided that perform the following operations: setting a memory buffer having contiguous memory blocks; obtaining a decision tree comprising nodes including split nodes and leaf nodes, wherein each of the split nodes includes at least two child nodes that are ordered according to a likelihood of accessing a child node after each of the split nodes; mapping the nodes onto respective blocks of the memory blocks, each of the memory blocks storing attributes of a corresponding one of the nodes, wherein each of the split nodes and any child nodes of each split node are mapped onto successive blocks, wherein ordered child nodes of a same one of the split nodes are mapped onto successive blocks; executing the nodes by processing the attributes of the nodes as accessed from the memory according to an order of the memory blocks in the memory buffer.

Abstract: An approach of accelerating inferences based on decision trees based on accessing one or more decision trees, wherein each decision tree of the decision trees accessed comprises decision tree nodes, including nodes grouped into one or more supersets of nodes designed for joint execution. For each decision tree of the decision trees accessed, the nodes are executed to obtain an outcome for the one or more decision trees, respectively. For each superset of the one or more supersets of said each decision tree, the nodes of each superset are jointly executed by: loading attributes of the nodes of each superset in a respective cache line of the cache memory processing said attributes from the respective cache line until an inference result is returned based on the one or more outcomes.

Abstract: The invention is notably directed to a computing system configured to perform linear algebraic operations. The computing system comprises a co-processing module comprising a co-processing unit. The co-processing unit comprises a parallel array of bit-serial processing units. The bit-serial processing units are adapted to perform the linear algebraic operations with variable precision. The invention further concerns a related computer implemented method and a related computer program product.

Abstract: Performing n-dimensional stencil processing may include providing a memory unit organized in memory banks for storing elements of an nD matrix, processing the matrix using a stencil vector unit in a first processing direction of the matrix tile-wise(/d). Data elements of the matrix can be equally distributed over the memory banks, and the number of memory banks can be equal to the number of data elements processable by the stencil vector unit in parallel, which is equal to the number of data elements in a width direction of one of the tiles. Additionally, the boundary elements can be grouped in the width direction of the tiles into a nD sub-matrix, and the nD sub-matrix can be processed equally to the processing the nD matrix orthogonal to the first processing direction.

Abstract: A method for accessing a binary data vector in a memory unit comprising a plurality of memory banks in which the binary data vector is stored in portions includes receiving a start address of the binary data vector and a power-of-2-stride elements of the data vector and determining offsets, wherein the offsets are determined by applying a plurality of bit-level XOR functions to the start address resulting in a Z vector, using the Z vector for accessing a mapping table, and shifting mapping table access results according to a power-of-2-stride of the binary data vector. Additionally, the method includes determining a sequence of portions of the binary data vector in the n memory banks depending on a binary equivalent value of the Z vector, and accessing the binary data vector in the n memory banks of the memory unit in parallel.

Abstract: Performing n-dimensional stencil processing may include providing a memory unit organized in memory banks for storing elements of an nD matrix, processing the matrix using a stencil vector unit in a first processing direction of the matrix tile-wise(/d). Data elements of the matrix can be equally distributed over the memory banks, and the number of memory banks can be equal to the number of data elements processable by the stencil vector unit in parallel, which is equal to the number of data elements in a width direction of one of the tiles. Additionally, the boundary elements can be grouped in the width direction of the tiles into a nD sub-matrix, and the nD sub-matrix can be processed equally to the processing the nD matrix orthogonal to the first processing direction.

Abstract: A method for accessing a binary data vector in a memory unit comprising a plurality of memory banks in which the binary data vector is stored in portions includes receiving a start address of the binary data vector and a power-of-2-stride elements of the data vector and determining offsets, wherein the offsets are determined by applying a plurality of bit-level XOR functions to the start address resulting in a Z vector, using the Z vector for accessing a mapping table, and shifting mapping table access results according to a power-of-2-stride of the binary data vector. Additionally, the method includes determining a sequence of portions of the binary data vector in the n memory banks depending on a binary equivalent value of the Z vector, and accessing the binary data vector in the n memory banks of the memory unit in parallel.

Abstract: A computing system comprising a central processing unit (CPU), a memory processor and a memory device comprising a data array and an index array. The computing system is configured to store data lines comprising data elements in the data array and to store index lines comprising a plurality of memory indices in the index array. The memory indices indicate memory positions of data elements in the data array with respect to a start address of the data array. There is further provided a related computer implemented method and a related computer program product.

Abstract: A method for performing enhanced pattern scanning includes the steps of: providing a three-dimensional memory structure including multiple physical memory elements; compiling multiple programmable finite state machines, each of the programmable finite state machines representing at least one deterministic finite automation data structure, the data structure being distributed over at least a subset of the physical memory elements; configuring a subset of the programmable finite state machines to operate in parallel on a same input data stream, while each of the subset of programmable finite state machines processes a different pattern subset; and providing a local result processor, the local result processor transferring at least a part of a match state from the deterministic finite automation data structures to corresponding registers within the local result processor, the part of the match state being manipulated being based on instructions embedded within the deterministic finite automation data structures.

Abstract: The invention is notably directed to a computing system configured to perform linear algebraic operations. The computing system comprises a co-processing module comprising a co-processing unit. The co-processing unit comprises a parallel array of bit-serial processing units. The bit-serial processing units are adapted to perform the linear algebraic operations with variable precision. The invention further concerns a related computer implemented method and a related computer program product.

Abstract: A reconfigurable computing device having a plurality of reconfigurable partitions and that is adapted to perform parallel processing of operand data by the partitions is provided. The computing system includes a memory device that is adapted to store configuration data to configure the partitions of the computing device, to store operand data to be processed by the configured partitions and to store processing results of the operand data. A programmable memory access processor having a predefined program is provided. The access processor performs address generation, address mapping and access scheduling for retrieving the configuration data from the memory unit, for retrieving the operand data from the memory unit and for storing the processing results in the memory unit. The access processor also transfers the configuration data from the memory unit to the computing device and transfers the operand data from the memory unit to the computing device.

Abstract: A reconfigurable computing device having a plurality of reconfigurable partitions and that is adapted to perform parallel processing of operand data by the partitions is provided. The computing system includes a memory device that is adapted to store configuration data to configure the partitions of the computing device, to store operand data to be processed by the configured partitions and to store processing results of the operand data. A programmable memory access processor having a predefined program is provided. The access processor performs address generation, address mapping and access scheduling for retrieving the configuration data from the memory unit, for retrieving the operand data from the memory unit and for storing the processing results in the memory unit. The access processor also transfers the configuration data from the memory unit to the computing device and transfers the operand data from the memory unit to the computing device.

Abstract: A computing system includes a host processor, an access processor having a command port, a near memory accelerator, and a memory unit. The system is adapted to run a software program on the host processor and to offload an acceleration task of the software program to the near memory accelerator. The system is further adapted to provide, via the command port, a first communication path for direct communication between the software program and the near memory accelerator, and to provide, via the command port and the access processor, a second communication path for indirect communication between the software program and the near memory accelerator. A related computer implemented method and a related computer program product are also disclosed.

Abstract: A computing system includes a host processor, an access processor having a command port, a near memory accelerator, and a memory unit. The system is adapted to run a software program on the host processor and to offload an acceleration task of the software program to the near memory accelerator. The system is further adapted to provide, via the command port, a first communication path for direct communication between the software program and the near memory accelerator, and to provide, via the command port and the access processor, a second communication path for indirect communication between the software program and the near memory accelerator. A related computer implemented method and a related computer program product are also disclosed.