Abstract: One example discloses an on-chip shielded device, including: a planar structure including a substrate and a passivation layer; an electrical component formed within the substrate and coupled to an input signal path and an output signal path; a first shielding element positioned above the electrical component and the passivation layer; and a second shielding element positioned above the electrical component, the passivation layer and the first shielding element.

Abstract: An RF package assembly includes a stacked package-on-package arrangement of a first substrate and a second substrate. Each of the first and second substrates include RF signal pads and ground pads. An interface region between the stacked substrates couples the RF signal pads and ground pads of the first substrate to corresponding pads of the second substrate. The interface region includes galvanic connection regions providing a galvanic connection between the each of the first substrate ground pads and each of the corresponding second substrate ground pads. The interface region includes dielectric regions between each of the first substrate RF signal pads and the corresponding second substrate RF signal pads so that RF signals transmitted between the two substrates are capacitively coupled.

Abstract: A flip chip device includes a substrate, an integrated circuit device, a mold compound, and a via. The substrate has a top side and a bottom side. The integrated circuit device is affixed to the bottom side of the substrate. The mold compound is affixed to the bottom side of the substrate. The via is affixed to the bottom side of the substrate. The via passes through the mold compound and is exposed at a bottom side of the mold compound. The via is coupled to a terminal of the integrated circuit device.

Abstract: A Radio Frequency, “RF”, component and a method of making the same. The component comprises a first electrically conductive signal member for conveying an RF signal and a second electrically conductive signal member for conveying an RF signal. The component also comprises a barrier located between the first signal member and the second signal member electromagnetically to shield the first and second signal members from each other. The barrier comprises a first row of electrically conductive shielding members spaced apart along a longitudinal axis of the first row, and a second row of electrically conductive shielding members spaced apart along a longitudinal axis of the second row. Each shielding member comprises a polyhedron. The shielding members of the first row are offset with respect to the shielding members of the second row to prevent a direct line of sight between the first signal member and the second signal member.

Abstract: A semiconductor device may include an antenna array and a grounding assembly configured to at least partially electrically shield the antenna array. The grounding assembly may include a first grounding layer comprising a first plurality of openings and a second grounding layer comprising a second plurality of openings. The second grounding layer may at least partially occlude the first plurality of openings of the first grounding layer when viewed from above the antenna array.

Abstract: An integrated circuit comprising a package, phased antenna array and die. The die comprises a plurality of unit cells, wherein each unit cell is divided into quadrants. Each quadrant comprises a receiver terminal located on a first axis, and a transmitter terminal located on a second axis, wherein the first axis is orthogonal to the second axis, and there is mirror symmetry between the nearest neighbour quadrants in the unit cell. The package comprises a plurality of pairs of feed lines, each pair of feed lines comprising a receiver feed line and a transmitter feed line. The receiver feed line is connected to one of the receiver terminals and the transmitter feed line is connected to the transmitter terminal in the same die quadrant. The receiver feed line is orthogonal to the transmitter feed line. Each antenna element is coupled to a respective pair of feed lines.

Abstract: A semiconductor device comprising a substrate, a first integrated circuit package mounted on the substrate, the first integrated circuit package comprising a first antenna sub-array having a uniform pitch, and a second integrated circuit package mounted on the substrate, the second integrated circuit package comprising a second antenna sub-array having a uniform pitch. The second integrated circuit package is mounted adjacent to the first integrated circuit package to form a multi-package module having an antenna array formed of the first antenna sub-array and the second antenna sub-array, wherein the antenna array has a uniform pitch. Also provided is a method of manufacturing a multi-package module and a method of providing package-to-package grounding.

Abstract: Embodiments of a packaged semiconductor device with no leads are disclosed. One embodiment includes a semiconductor chip and a no leads package structure defining a boundary and having a bottom surface and includes three or more pads exposed at the bottom surface of the package structure. Each of the pads is located in a single inline row.

Abstract: Embodiments of a packaged semiconductor device with no leads are disclosed. One embodiment includes a semiconductor chip and a no leads package structure defining a boundary and having a bottom surface and includes three or more pads exposed at the bottom surface of the package structure. Each of the pads is located in a single inline row.