Patents by Inventor Janardhan H. Satyanarayana

Janardhan H. Satyanarayana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11671194
    Abstract: Technologies for high-precision timestamping of data packets is disclosed. Several sources of errors that may arise when timestamping the arrival or sending of data packets may be determined and corrected, including variable latencies, semi-static latencies, and fixed latencies. In the illustrative embodiment, a variable latency may arise due to a phase difference between a clock of a network interface card and a system clock. When a trigger pattern is detected, such as the start of a data packet, a trigger may be sent from a circuit synchronized to the clock of the network interface card to a circuit synchronized to the system clock. The phase difference between the edge of the clock on the network interface card and the edge of the clock of the system clock leads to an error in the timestamp value. Determining the phase difference allows for the error in the timestamp value to be corrected.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: June 6, 2023
    Assignee: Intel Corporation
    Inventors: Mark A. Bordogna, Janardhan H. Satyanarayana, Larry N. Wakeman, Robert G. Southworth, Mika Nystroem
  • Patent number: 11546241
    Abstract: Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: January 3, 2023
    Assignee: Intel Corporation
    Inventors: Yoni Landau, Janardhan H. Satyanarayana, Assaf Benhamou, Mark A. Bordogna
  • Publication number: 20220150149
    Abstract: Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.
    Type: Application
    Filed: October 18, 2021
    Publication date: May 12, 2022
    Inventors: Yoni Landau, Janardhan H. Satyanarayana, Assaf BENHAMOU, Mark A. Bordogna
  • Publication number: 20220077946
    Abstract: Technologies for high-precision timestamping of data packets is disclosed. Several sources of errors that may arise when timestamping the arrival or sending of data packets may be determined and corrected, including variable latencies, semi-static latencies, and fixed latencies. In the illustrative embodiment, a variable latency may arise due to a phase difference between a clock of a network interface card and a system clock. When a trigger pattern is detected, such as the start of a data packet, a trigger may be sent from a circuit synchronized to the clock of the network interface card to a circuit synchronized to the system clock. The phase difference between the edge of the clock on the network interface card and the edge of the clock of the system clock leads to an error in the timestamp value. Determining the phase difference allows for the error in the timestamp value to be corrected.
    Type: Application
    Filed: November 16, 2021
    Publication date: March 10, 2022
    Applicant: Intel Corporation
    Inventors: Mark A. Bordogna, Janardhan H. Satyanarayana, Larry N. Wakeman, Robert G. Southworth, Mika Nystroem
  • Patent number: 11212024
    Abstract: Technologies for high-precision timestamping of data packets is disclosed. Several sources of errors that may arise when timestamping the arrival or sending of data packets may be determined and corrected, including variable latencies, semi-static latencies, and fixed latencies. In the illustrative embodiment, a variable latency may arise due to a phase difference between a clock of a network interface card and a system clock. When a trigger pattern is detected, such as the start of a data packet, a trigger may be sent from a circuit synchronized to the clock of the network interface card to a circuit synchronized to the system clock. The phase difference between the edge of the clock on the network interface card and the edge of the clock of the system clock leads to an error in the timestamp value. Determining the phase difference allows for the error in the timestamp value to be corrected.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: December 28, 2021
    Assignee: Intel Corporation
    Inventors: Mark A. Bordogna, Janardhan H. Satyanarayana, Larry N. Wakeman, Robert G. Southworth, Mika Nystroem
  • Patent number: 11153191
    Abstract: Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: October 19, 2021
    Assignee: Intel Corporation
    Inventors: Yoni Landau, Janardhan H. Satyanarayana, Assaf Benhamou, Mark A. Bordogna
  • Publication number: 20210203428
    Abstract: Technologies for high-precision timestamping of data packets is disclosed. Several sources of errors that may arise when timestamping the arrival or sending of data packets may be determined and corrected, including variable latencies, semi-static latencies, and fixed latencies. In the illustrative embodiment, a variable latency may arise due to a phase difference between a clock of a network interface card and a system clock. When a trigger pattern is detected, such as the start of a data packet, a trigger may be sent from a circuit synchronized to the clock of the network interface card to a circuit synchronized to the system clock. The phase difference between the edge of the clock on the network interface card and the edge of the clock of the system clock leads to an error in the timestamp value. Determining the phase difference allows for the error in the timestamp value to be corrected.
    Type: Application
    Filed: April 7, 2017
    Publication date: July 1, 2021
    Inventors: Mark A. BORDOGNA, Janardhan H. SATYANARAYANA, Larry N. WAKEMAN, Robert G. SOUTHWORTH, Mika NYSTROEM
  • Publication number: 20190044839
    Abstract: Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.
    Type: Application
    Filed: March 30, 2018
    Publication date: February 7, 2019
    Inventors: Yoni Landau, Janardhan H. Satyanarayana, Assaf Benhamou, Mark A. Bordogna