Patents by Inventor Janardhan SATYANARAYANA

Janardhan SATYANARAYANA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11805042
    Abstract: Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: October 31, 2023
    Assignee: Intel Corporation
    Inventors: Yoni Landau, Janardhan Satyanarayana, Assaf Benhamou, Mark Bordogna
  • Patent number: 11711159
    Abstract: In a transceiver, the accuracy of a packet time stamp can be improved by compensating for errors introduced by processing of the packet. A received packet can be received via multiple lanes. A packet time stamp can be measured using a start of frame delimiter (SFD). A last arriving lane can be used to provide a recovered clock signal. A phase offset between the recovered clock signal and the system clock of the transceiver can be used to adjust the time stamp. A position of the SFD within a data block can be used to adjust the time stamp. A position of the data block within a combined group of data blocks can be used to adjust the time stamp. Also, a serializer-deserializer delay associated with the last arriving lane can be used to adjust the time stamp.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: July 25, 2023
    Assignee: Intel Corporation
    Inventors: Mark Bordogna, Janardhan Satyanarayana, Yoni Landau, Diwakar Suvvari
  • Publication number: 20230016505
    Abstract: Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.
    Type: Application
    Filed: September 20, 2022
    Publication date: January 19, 2023
    Applicant: Intel Corporation
    Inventors: Yoni Landau, Janardhan Satyanarayana, Assaf Benhamou, Mark Bordogna
  • Patent number: 11265096
    Abstract: In a transceiver, the accuracy of a packet time stamp can be improved by compensating for errors introduced by processing of the packet. A received packet can be received via multiple lanes. A packet time stamp can be measured using a start of frame delimiter (SFD). A last arriving lane can be used to provide a recovered clock signal. A phase offset between the recovered clock signal and the system clock of the transceiver can be used to adjust the time stamp. A position of the SFD within a data block can be used to adjust the time stamp. A position of the data block within a combined group of data blocks can be used to adjust the time stamp. Also, a serializer-deserializer delay associated with the last arriving lane can be used to adjust the time stamp.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Mark Bordogna, Janardhan Satyanarayana, Yoni Landau, Diwakar Suvvari
  • Publication number: 20210152271
    Abstract: In a transceiver, the accuracy of a packet time stamp can be improved by compensating for errors introduced by processing of the packet. A received packet can be received via multiple lanes. A packet time stamp can be measured using a start of frame delimiter (SFD). A last arriving lane can be used to provide a recovered clock signal. A phase offset between the recovered clock signal and the system clock of the transceiver can be used to adjust the time stamp. A position of the SFD within a data block can be used to adjust the time stamp. A position of the data block within a combined group of data blocks can be used to adjust the time stamp. Also, a serializer-deserializer delay associated with the last arriving lane can be used to adjust the time stamp.
    Type: Application
    Filed: December 24, 2020
    Publication date: May 20, 2021
    Inventors: Mark BORDOGNA, Janardhan SATYANARAYANA, Yoni LANDAU, Diwakar SUVVARI
  • Publication number: 20190273571
    Abstract: In a transceiver, the accuracy of a packet time stamp can be improved by compensating for errors introduced by processing of the packet. A received packet can be received via multiple lanes. A packet time stamp can be measured using a start of frame delimiter (SFD). A last arriving lane can be used to provide a recovered clock signal. A phase offset between the recovered clock signal and the system clock of the transceiver can be used to adjust the time stamp. A position of the SFD within a data block can be used to adjust the time stamp. A position of the data block within a combined group of data blocks can be used to adjust the time stamp. Also, a serializer-deserializer delay associated with the last arriving lane can be used to adjust the time stamp.
    Type: Application
    Filed: May 13, 2019
    Publication date: September 5, 2019
    Inventors: Mark BORDOGNA, Janardhan SATYANARAYANA, Yoni LANDAU, Diwakar SUVVARI