Patents by Inventor Jane-Bai Lai

Jane-Bai Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7208415
    Abstract: A plasma treatment method which is capable of extending the MTF (mean-time-to-failure) of metal interconnects fabricated on a semiconductor wafer substrate, is disclosed. The invention includes providing a trench typically in a dielectric layer on a substrate; depositing a metal in the trench; and exposing the metal to a nitrogen-based plasma. The plasma-treatment step accelerates grain growth and re-orients the grains in the metal to a closely-packed crystal orientation texture which approaches or approximates the <111> crystal orientation texture of copper.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: April 24, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jane-Bai Lai, Yi-Lung Cheng
  • Publication number: 20060003486
    Abstract: A plasma treatment method which is capable of extending the MTF (mean-time-to-failure) of metal interconnects fabricated on a semiconductor wafer substrate, is disclosed. The invention includes providing a trench typically in a dielectric layer on a substrate; depositing a metal in the trench; and exposing the metal to a nitrogen-based plasma. The plasma-treatment step accelerates grain growth and re-orients the grains in the metal to a closely-packed crystal orientation texture which approaches or approximates the <111>crystal orientation texture of copper.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventors: Jane-Bai Lai, Yi-Lung Cheng
  • Patent number: 6780783
    Abstract: A method of etching a low dielectric constant material with an aqueous solution of hydrofluoric acid and hydrochloric acid. The etching solution is particularly useful on low dielectric constant materials that are water repulsive or hydrophobic. The weight ratio of hydrofluoric acid to hydrochloric acid in the aqueous solution ranges from 1:3 to 4:1.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: August 24, 2004
    Assignee: Taiwan SEmiconductor Manufacturing Co., Ltd.
    Inventors: Jane-Bai Lai, Pei-Fen Chou
  • Patent number: 6753259
    Abstract: Cu, for its rather low resistivity, will be widely used in sub-quarter micron meter ULSI devices. However, it is well known that Cu is easy to be corroded as exposed in air. In packaging of chips the bonding pads making of Cu will thus oxides. In addition, the reaction between Au-ball and Cu pads is very poor. On the other hand, a native AlOx layer, about 3-4 nm in thickness, will form as Al exposes in air; the formed layer is inert and is capable of protecting Al from corrosion. Furthermore, the reaction between Au-ball and Al was very well. Therefore, with the methods of the present invention, Al or AlCu as a glue and protection layer is implemented on Cu bonding pads for successful Au wiring.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: June 22, 2004
    Inventors: Syun-Ming Jang, Mong-Song Liang, Chen-Hua Yu, Chung-Shi Liu, Jane-Bai Lai
  • Patent number: 6660655
    Abstract: A method and a solution for preparing SEM samples comprising low-K dielectric materials. The process begins by providing a SEM sample comprising low-K dielectric material and silicon oxide material. A solution is formed for preparing (staining and etching) the SEM sample by adding NH4F (s) to a solution comprising CH3COOH having a concentration of about 98% at a ratio of about 1 g NH4F (s):20 ml CH3COOH, then stirring until the NH4F (s) is thoroughly dissolved. Alternatively, the NH4F (s) can be added to a solution comprising HNO3 having a concentration of about 70% and CH3COOH having a concentration of about 98%, with a volume ratio of about 15 ml HNO3:20 ml CH3COOH. The NH4F (s) is added at a ratio of about 1 g NH4F (s):35 ml CH3COOH and HNO3, and stirred until the NH4F (s) is thoroughly dissolved. The SEM sample is then etched in this solution for about 3 seconds, whereby the low-K dielectric material and silicon oxide material have similar etch rates with good selectivity to metals.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: December 9, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Jane-Bai Lai
  • Publication number: 20030157802
    Abstract: A method and a solution for preparing SEM samples comprising low-K dielectric materials. The process begins by providing a SEM sample comprising low-K dielectric material and silicon oxide material. A solution is formed for preparing (staining and etching) the SEM sample by adding NH4F (s) to a solution comprising CH3COOH having a concentration of about 98% at a ratio of about 1 g NH4F (s):20 ml CH3COOH, then stirring until the NH4F (s) is thoroughly dissolved. Alternatively, the NH4F (s) can be added to a solution comprising HNO3 having a concentration of about 70% and CH3COOH having a concentration of about 98%, with a volume ratio of about 15 ml HNO3:20 ml CH3COOH. The NH4F (s) is added at a ratio of about 1 g NH4F (s):35 ml CH3COOH and HNO3, and stirred until the NH4F (s) is thoroughly dissolved. The SEM sample is then etched in this solution for about 3 seconds, whereby the low-K dielectric material and silicon oxide material have similar etch rates with good selectivity to metals.
    Type: Application
    Filed: March 17, 2003
    Publication date: August 21, 2003
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventor: Jane-Bai Lai
  • Publication number: 20030049938
    Abstract: A method of etching a low dielectric constant material with an aqueous solution of hydrofluoric acid and hydrochloric acid. The etching solution is particularly useful on low dielectric constant materials that are water repulsive or hydrophobic. The weight ratio of hydrofluoric acid to hydrochloric acid in the aqueous solution ranges from 1:3 to 4:1.
    Type: Application
    Filed: August 29, 2001
    Publication date: March 13, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Jane-Bai Lai, Pei-Fen Chou
  • Patent number: 6423625
    Abstract: Cu, for its rather loe resistivity, will be widely used in sub-quarter micron meter ULSI devices. However, it is well known that Cu is easy to be corroded as exposed in air. In packaging of chips the bonding pads making of Cu will thus oxides. In addition, the reaction between Au-ball and Cu pads is very poor. On the other hand, a native AlOx layer, about 3-4 nm in thickness, will form as Al exposes in air; the formed layer is inert and is capable of protecting Al from corrosion. Furthermore, the reaction between Au-ball and Al was very well. Therefore, with the methods of the present invention, Al or AlCu as a glue and protection layer is implemented on Cu bonding pads for successful Au wiring.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: July 23, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Syun-Ming Jang, Mong-Song Liang, Chen-Hua Yu, Chung-Shi Liu, Jane-Bai Lai
  • Publication number: 20020086533
    Abstract: Cu, for its rather low resistivity, will be widely used in sub-quarter micron meter ULSI devices. However, it is well known that Cu is easy to be corroded as exposed in air. In packaging of chips the bonding pads making of Cu will thus oxides. In addition, the reaction between Au-ball and Cu pads is very poor. On the other hand, a native AlOx layer, about 3-4 nm in thickness, will form as Al exposes in air; the formed layer is inert and is capable of protecting Al from corrosion. Furthermore, the reaction between Au-ball and Al was very well. Therefore, with the methods of the present invention, Al or AlCu as a glue and protection layer is implemented on Cu bonding pads for successful Au wiring.
    Type: Application
    Filed: October 5, 2001
    Publication date: July 4, 2002
    Inventors: Syun-Ming Jang, Mong-Song Liang, Chen-Hua Yu, Chung-Shi Liu, Jane-Bai Lai
  • Patent number: 6399487
    Abstract: An improved SALICIDE process is described wherein the transformation temperature to a lower resistivity suicide structure is reduced by first coating with a layer of a silicon-germanium alloy prior to the deposition of the titanium layer. Provided there is at least 40 atomic percent of germanium in the alloy a second RTA at a temperature no higher than about 650° C. may be effectively used. The resulting ternary alloy has a resistivity of about 15-20 microhm cm which corresponds to a sheet resistance of about 3-3.5 ohms per square. The ability to achieve low sheet resistance after annealing at such a low temperature becomes increasingly more important as device dimensions decrease since the second RTA becomes increasingly more likely to result in agglomeration of the silicidelayer.
    Type: Grant
    Filed: December 28, 1998
    Date of Patent: June 4, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jane-Bai Lai, Lih-Juan Chen, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 6136680
    Abstract: A method of forming an interconnect, comprising the following steps. A semiconductor structure is provided that has an exposed first metal contact and a dielectric layer formed thereover. An FSG layer having a predetermined thickness is then formed over the dielectric layer. A trench, having a predetermined width, is formed within the FSG layer and the dielectric layer exposing the first metal contact. A barrier layer, having a predetermined thickness, may be formed over the FSG layer and lining the trench side walls and bottom. A metal, preferably copper, is then deposited on the barrier layer to form a copper layer, having a predetermined thickness, over said barrier layer covered FSG layer, filling the lined trench and blanket filling the barrier layer covered FSG layer. The copper layer, and the barrier layer on said upper surface of said FSG layer, are planarized, exposing the upper surface of the FSG layer and forming a planarized copper filled trench.
    Type: Grant
    Filed: January 21, 2000
    Date of Patent: October 24, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jane-Bai Lai, Chung-Shi Liu, Tien-I Bao, Syun-Ming Jang, Chung-Long Chang, Hui-Ling Wang, Szu-An Wu, Wen-Kung Cheng, Chun-Ching Tsan, Ying-Lang Wang
  • Patent number: 6083829
    Abstract: A method for fabricating a copper interconnect structure, using a low resistivity Cu.sub.3 Ge intermetallic layer, as an adhesive layer, has been developed. Following an in situ, CVD of a titanium nitride barrier layer, a germanium layer, and a copper layer, an anneal procedure is used to form the Cu.sub.3 Ge intermetallic layer, with the intermetallic layer, located between the underlying titanium nitride barrier layer, and the overlying copper layer. The Cu.sub.3 Ge intermetallic layer can also be formed in situ, during deposition, if the deposition temperature exceeds 150.degree. C. Cu.sub.3 Ge layer exhibits a resistivity of about 5E-6 ohm - cm. A second iteration of this invention allows a thick copper layer to be plated on a thin copper seed layer, only on the top surface of a semiconductor substrate. This iteration, also incorporating the low resistivity, Cu.sub.3 Ge intermetallic, and the adhesive layer, prevents copper from being plated on the beveled edge of the semiconductor substrate.
    Type: Grant
    Filed: May 22, 1998
    Date of Patent: July 4, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jane-Bai Lai, Lih-Juann Chen, Chung-Shi Liu, Chen-Hua Douglas Yu
  • Patent number: 6015749
    Abstract: A method for fabricating a copper interconnect structure, using a Cu.sub.3 Ge intermetallic layer, as an adhesive layer, has been developed. Following the deposition of a copper seed layer, an ion implantation procedure is performed, placing germanium ions in a copper seed layer. After deposition of a thick copper layer, an anneal cycle, performed before or after deposition of the thick copper layer, is used to create a Cu.sub.3 Ge intermetallic layer at the interface between a copper seed layer and a titanium nitride barrier layer. A second embodiment of this invention uses a tilted, germanium ion implantation procedure, used to avoid the placement of germanium ions in a copper seed layer, at the bottom of a contact hole, thus avoiding possible implantation damage, to active device regions, exposed in the bottom of the contact hole.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: January 18, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chung-Shi Liu, Chen-Hua Douglas Yu, Jane-Bai Lai, Lih-Juann Chen