Patents by Inventor Jane Hui

Jane Hui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9054107
    Abstract: A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: June 9, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Fan Zhang, Xiaomei Bu, Jane Hui, Tae Jong Lee, Liang Choo Hsia
  • Publication number: 20140084486
    Abstract: A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material.
    Type: Application
    Filed: December 2, 2013
    Publication date: March 27, 2014
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Fan ZHANG, Xiaomei BU, Jane HUI, Tae Jong LEE, Liang Choo HSIA
  • Patent number: 8598031
    Abstract: A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: December 3, 2013
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Fan Zhang, Xiaomei Bu, Jane Hui, Tae Jong Lee, Liang Choo Hsia
  • Publication number: 20110159154
    Abstract: The invention relates to methods of producing jelly confectionery products, and to jelly confectionery products themselves. The centre-filled jelly confectionery comprises—a centre filling, —a casing, and —a backing layer, wherein the backing layer has a different visual appearance compared to the casing. According to one embodiment, the centre filling is coloured, the casing comprises a colouring agent, and the backing layer comprises said colouring agent of the casing, at a concentration that is greater than in the casing. According to another embodiment, the centre filling is coloured, the casing is uncoloured, and the backing layer is coloured.
    Type: Application
    Filed: April 14, 2009
    Publication date: June 30, 2011
    Inventor: Jane Hui Ching Ang
  • Publication number: 20110074039
    Abstract: A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material.
    Type: Application
    Filed: September 28, 2009
    Publication date: March 31, 2011
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Fan ZHANG, Xiaomei BU, Jane HUI, Tae Jong LEE, Liang Choo HSIA
  • Patent number: 7585768
    Abstract: A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: September 8, 2009
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Xiaomei Bu, Alex See, Fan Zhang, Jane Hui, Tae Jong Lee, Liang Choo Hsia
  • Publication number: 20070293039
    Abstract: A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.
    Type: Application
    Filed: June 16, 2006
    Publication date: December 20, 2007
    Inventors: Xiaomei Bu, Alex See, Fan Zhang, Jane Hui, Tae Jong Lee, Liang Choo Hsia