Abstract: An organic light emitting diode (OLED) and an organic light emitting device (e.g., a display device or a lighting device) comprising the OLED are described. An emissive layer includes a red emitting material layer, a yellow-green emitting material layer and a green emitting material layer disposed sequentially between two electrodes, where each of the emitting material layers has controlled thickness and includes at least one host with controlled energy level. The OLED and the organic light emitting device have improved pure color luminous efficiency and color gamut, as well as luminous efficiency and luminous lifespan.

Abstract: An organic light emitting diode (OLED) and an organic light emitting device comprising the OLED are described. The OLED can comprise a first electrode; a second electrode facing the first electrode; and a first emitting part (including a first blue emitting layer and a second blue emitting layer), which is positioned between the first and second electrode. The second blue emitting layer is positioned between the first blue emitting layer and the second electrode and contacting the first blue emitting layer. The first blue emitting layer includes a first host and a first dopant, and the second blue emitting layer includes a second host and a second dopant, wherein the first host is a pyrene derivative, and the second host is an anthracene derivative. An organic light emitting device can include the OLED, and can be a display device or a lighting device.

Abstract: A display device can a display area and a non-display area adjacent to the display area disposed on a substrate, and a first thin film transistor disposed in the display area and including a first semiconductor pattern, a first gate electrode, a first source electrode and a first drain electrode. The display device further includes an emitting element disposed in the display area and connected to the first thin film transistor, and a first lower conductive pattern disposed under the first semiconductor pattern. The first lower conductive pattern can overlap with the first semiconductor pattern and has at least one uneven pattern on a top surface thereof. Further, the first lower conductive pattern is connected to one of the first source electrode and the first drain electrode.

Abstract: A display apparatus can include a first thin-film transistor including a first active layer having a first polysilicon material, a first gate electrode overlapping the first active layer, a first electrode and a second electrode; a second thin-film transistor including a second active layer having an oxide semiconductor, a second gate electrode overlapping the second active layer, a third electrode and a fourth electrode; and a first emitting electrode of a light emitting element electrically connected to the second electrode of the first thin-film transistor. Also, one end of the first active layer having the first polysilicon material is electrically connected to one or the other end of the second active layer having the oxide semiconductor.

Abstract: A display apparatus including a first thin-film transistor, a second thin-film transistor and a third thin-film transistor is provided. The first thin-film transistor includes a first active layer composed of a polysilicon material, a first gate electrode overlapping the first active layer such that a first gate insulating layer is interposed therebetween, a first source electrode and a first drain electrode. The first gate electrode includes n layers. The first source electrode and the first drain electrode are connected to the first active layer. The second thin-film transistor includes a second active layer composed of a polysilicon material, a second gate electrode overlapping the second active layer such that a first gate insulating layer is interposed therebetween, a second source electrode and a second drain electrode. The second gate electrode includes n+1 layers. The second source electrode and the second drain electrode are connected to the second active layer.

Abstract: An organic light-emitting display device and thin-film transistor array substrate is disclosed. The organic light-emitting display device is capable of reducing the size of a thin-film transistor disposed in a sub-pixel in order to realize a high-definition organic light-emitting display device is disclosed. Conductive regions and non-conductive regions are combined in each of a source region and a drain region, such that the size of a channel is increased, for example, substantially increased. Thus, it is possible to realize a high-definition organic light-emitting display device. Furthermore, s-factor value of a driving thin-film transistor is increased, and the operational speed of a switching thin-film transistor is increased.

Abstract: A display apparatus may include at least one switching thin film transistor and a driving thin film transistor, which are disposed on a device substrate. The driving thin film transistor may include a driving semiconductor pattern made of an oxide semiconductor. A light-blocking pattern may be disposed between the device substrate and the driving semiconductor pattern. The light-blocking pattern may be disposed close to the driving semiconductor pattern. Thus, in the display apparatus, a current variation value according to a voltage applied to the driving gate electrode of the driving thin film transistor may be reduced, without changing the characteristics of the switching thin film transistor. Thereby, in the display apparatus, the occurrence of a spot in low grayscale may be prevented.

Abstract: A display apparatus including a first thin-film transistor, a second thin-film transistor and a third thin-film transistor is provided. The first thin-film transistor includes a first active layer composed of a polysilicon material, a first gate electrode overlapping the first active layer such that a first gate insulating layer is interposed therebetween, a first source electrode and a first drain electrode. The first gate electrode includes n layers. The first source electrode and the first drain electrode are connected to the first active layer. The second thin-film transistor includes a second active layer composed of a polysilicon material, a second gate electrode overlapping the second active layer such that a first gate insulating layer is interposed therebetween, a second source electrode and a second drain electrode. The second gate electrode includes n+1 layers. The second source electrode and the second drain electrode are connected to the second active layer.

Abstract: System and method are provided for transferring electrical energy among multiple electrical energy storage devices via a differential power bus and a capacitive load switched-mode power supply. The switched-mode power supply transfers the electrical energy between the load capacitor and the differential power bus to which the electrical energy storage devices (e.g., rechargeable batteries and/or capacitors connected in parallel or series or combinations of both) are electrically connected via bus switches. As a result, electrical energy is efficiently transferred and distributed among the electrical energy storage devices.

Abstract: System and method are provided for transferring electrical energy among multiple electrical energy storage devices via multiple differential power buses and capacitive load switched-mode power supplies. The switched-mode power supplies transfer the electrical energy between the load capacitors and the differential power buses to which the electrical energy storage devices (e.g., rechargeable batteries and/or capacitors connected in parallel or series or combinations of both) are electrically connected via bus switches. As a result, electrical energy is efficiently transferred and distributed among the electrical energy storage devices.

Abstract: System and method are provided for transferring electrical energy among multiple electrical energy storage devices via multiple differential power buses and capacitive load switched-mode power supplies. The switched-mode power supplies transfer the electrical energy between the load capacitors and the differential power buses to which the electrical energy storage devices (e.g., rechargeable batteries and/or capacitors connected in parallel or series or combinations of both) are electrically connected via bus switches. As a result, electrical energy is efficiently transferred and distributed among the electrical energy storage devices.

Abstract: System and method are provided for transferring electrical energy among multiple electrical energy storage devices via a differential power bus and a capacitive load switched-mode power supply. The switched-mode power supply transfers the electrical energy between the load capacitor and the differential power bus to which the electrical energy storage devices (e.g., rechargeable batteries and/or capacitors connected in parallel or series or combinations of both) are electrically connected via bus switches. As a result, electrical energy is efficiently transferred and distributed among the electrical energy storage devices.

Abstract: A dipole oscillation tank circuit includes a first capacitive structure, an inductive structure, and a second capacitive structure connected in series. The tank circuit transfers electric energy back and forth between the capacitive structures in dipole oscillation cycles. A renewal circuit injects energy into the tank circuit to replenish energy lost during the oscillation cycles. A switch is connected in parallel across the first capacitive structure and in parallel across the inductive structure and the second capacitive structure. During one phase of the oscillation cycles, the switch is opened for current to flow through the first capacitive structure and the inductive structure, and then closed to bypass the first capacitive structure. During another phase of the oscillation cycles, the switch is closed to bypass the first capacitive structure and then opened for current to flow through the first capacitive structure and the inductive structure.

Abstract: In accordance with the presently claimed invention, circuitry and a method are provided for using a voltage to drive a light emitting diode (LED) load including one or more LEDs. The incoming voltage is switched and inductively conditioned to drive the LED load in such a manner as to cause the LED load to appear as a substantially linear resistive load, thereby maximizing the power factor presented to an AC power grid serving as the source of the input voltage.

Abstract: An analog system consists of a multitude of interconnected components. Design of such a system involves optimization of the component parameters to achieve a target behavior, collectively called specification. The present invention provides a generic cost function for analog design optimization. It also provides cost surface modeling to speed up the optimization. The cost function compares the behavior of a design to a quantitative specification, which can be a ‘golden’ reference behavior (specification), and measures the error cost, an index of the behavioral discrepancy. That is, the target behavior is explicitly embedded in the cost function. By using the cost function, one can readily qualify a design and thereby identify good/optimum designs.

Abstract: An Algorithmic Reactive Testbench (ART) system is provided for the simulation/verification of an analog integrated circuit design. The ART system is a high level simulation/verification environment with a user program in which one or more analog testbenches are instantiated and operated as prescribed in an algorithmic reactive testbench program, and the properties of the unit testbenches (test objects) can be influenced by prior analysis of themselves or other tests. The test object may also contain various properties including information reflecting the status of the test object. The modification of a property of a test object is an act of communication in the ART system from the algorithmic reactive testbench program to the test object.

Abstract: An analog system consists of a multitude of interconnected components. Design of such a system involves optimization of the component parameters to achieve a target behavior, collectively called specification. The present invention provides a generic cost function for analog design optimization. It also provides cost surface modeling to speed up the optimization. The cost function compares the behavior of a design to a quantitative specification, which can be a ‘golden’ reference behavior (specification), and measures the error cost, an index of the behavioral discrepancy. That is, the target behavior is explicitly embedded in the cost function. By using the cost function, one can readily qualify a design and thereby identify good/optimum designs.

Abstract: An Algorithmic Reactive Testbench (ART) system is provided. The ART system is a high level verification environment with a user program in which on or more analog testbenches are instantiated and operated as prescribed in the program algorithm, and the properties of the unit testbenches (test objects) can be influenced by prior analysis of themselves or other tests. The results of the analysis may also affect the flow of the program itself. In the ART system, modification of the properties of a unit testbench occurs separately in the user program after definition of the unit testbench in the program (test object). A test object is a representation of a unit testbench along with its complete simulation setup and all associated data for the simulation. The test object may also contain various properties including information reflecting the status of the test object. The modification of a property of a test object is an act of communication in the ART system from the ART program to the test object.