Abstract: The present invention relates to an image display device and a method for operating same. According to an embodiment of the present invention, a method for operating an image display device uses a remote controller, and comprises the steps of: displaying a pointer in a first area of a display; receiving movement coordinate information of the pointer from the remote controller; restoring the first area using a prestored image when the first area does not overlap a second area where a pointer is displayed, based on the movement coordinate information; storing an image of the second area; and displaying a pointer in the second area. This enables the pointer of the remote controller to be easily displayed.

Abstract: A method of forming through silicon vias (TSVs) uses a low-k dielectric material as a via insulating layer to thereby improve step coverage and minimize resistive capacitive (RC) delay. To this end, the method includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.

Abstract: Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer.

Abstract: A method of manufacturing a semiconductor device includes: forming a trench for forming buried type wires by etching a substrate; forming first and second oxidation layers on a bottom of the trench and a wall of the trench, respectively; removing a part of the first oxidation layer and the entire second oxidation layer; and forming the buried type wires on the wall of the trench by performing a silicide process on the wall of the trench from which the second oxidation layer is removed. As a result, the buried type wires are insulated from each other.

Abstract: A method of forming through silicon vias (TSVs) includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.

Abstract: A method of forming a buried gate electrode prevents voids from being formed in a silicide layer of the gate electrode. The method begins by forming a trench in a semiconductor substrate, forming a conformal gate oxide layer on the semiconductor in which the trench has been formed, forming a first gate electrode layer on the gate oxide layer, forming a silicon layer on the first gate electrode layer to fill the trench. Then, a portion of the first gate electrode layer is removed to form a recess which exposed a portion of a lateral surface of the silicon layer. A metal layer is then formed on the semiconductor substrate including on the silicon layer. Next, the semiconductor substrate is annealed while the lateral surface of the silicon layer is exposed to form a metal silicide layer on the silicon layer.

Abstract: A method of forming through silicon vias (TSVs) includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.

Abstract: Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer.

Abstract: The present invention relates to a method and a kit for diagnosis of semen quality (motility and concentration) through observation of color change visible with the naked eye in a solution combining methylene blue and sperm. The invention comprises a method for semen diagnosis using color coding (with a standard color table) charting the various colors the semen may change into, and a diagnostic it for testing semen using said method. When combined with methylene blue, healthier and more active sperm fades the original blue color more rapidly due to respiration activity by the sperm, which allows for semen quality evaluation. The above principle are adapted to kit from inside a tube which encases a methylene blue solution into which sample semen is introduced for easy evaluation.

Abstract: A plurality of spaced-apart conductor structures is formed on a semiconductor substrate, each of the conductor structures including a conductive layer. Insulating spacers are formed on sidewalls of the conductor structures. An interlayer-insulating film that fills gaps between adjacent ones of the insulating spacers is formed. Portions of the interlayer-insulating layer are removed to expose upper surfaces of the conductive layers. Respective epilayers are grown on the respective exposed upper surfaces of the conductive layers and respective metal silicide layers are formed from the respective epilayers.

Abstract: In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.

Abstract: A method of manufacturing a semiconductor device includes: forming a trench for forming buried type wires by etching a substrate; forming first and second oxidation layers on a bottom of the trench and a wall of the trench, respectively; removing a part of the first oxidation layer and the entire second oxidation layer; and forming the buried type wires on the wall of the trench by performing a silicide process on the wall of the trench from which the second oxidation layer is removed. As a result, the buried type wires are insulated from each other.

Abstract: A method of forming a buried gate electrode prevents voids from being formed in a silicide layer of the gate electrode. The method begins by forming a trench in a semiconductor substrate, forming a conformal gate oxide layer on the semiconductor in which the trench has been formed, forming a first gate electrode layer on the gate oxide layer, forming a silicon layer on the first gate electrode layer to fill the trench. Then, a portion of the first gate electrode layer is removed to form a recess which exposed a portion of a lateral surface of the silicon layer. A metal layer is then formed on the semiconductor substrate including on the silicon layer. Next, the semiconductor substrate is annealed while the lateral surface of the silicon layer is exposed to form a metal silicide layer on the silicon layer.

Abstract: In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.

Abstract: A semiconductor memory device, e.g., a charge trapping type non-volatile memory device, may include a charge trapping structure formed in a first area of a substrate and a gate structure formed in a second area of the substrate. The charge trapping structure may include a tunnel oxide layer pattern, a charge trapping layer pattern and a dielectric layer pattern of aluminum-containing tertiary metal oxide. The gate structure may include a gate oxide layer pattern, a polysilicon layer pattern and an ohmic layer pattern of aluminum-containing tertiary metal silicide. A first electrode and a second electrode may be formed on the charge trapping structure. A lower electrode and an upper electrode may be provided on the gate structure. The dielectric layer pattern may have a higher dielectric constant, and the ohmic layer pattern may have improved thermal stability, thereby enhancing programming and erasing operations of the charge trapping type non-volatile memory device.

Abstract: A plurality of spaced-apart conductor structures is formed on a semiconductor substrate, each of the conductor structures including a conductive layer. Insulating spacers are formed on sidewalls of the conductor structures. An interlayer-insulating film that fills gaps between adjacent ones of the insulating spacers is formed. Portions of the interlayer-insulating layer are removed to expose upper surfaces of the conductive layers. Respective epilayers are grown on the respective exposed upper surfaces of the conductive layers and respective metal silicide layers are formed from the respective epilayers.

Abstract: In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.

Abstract: Embodiments of the present invention include semiconductor devices that can be made with relatively low resistance, and methods of forming the semiconductor devices. A resistance reducing layer is formed between a polysilicon layer and a metal layer. As a result, an interface resistance between the polysilicon layer and the metal layer is greatly reduced and a distribution of the interface resistance is very uniform. As a result, a conductive structure including the resistance reducing layer has a greatly reduced sheet resistance to improve electrical characteristics of a semiconductor device having the conductive structure.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate and a doped conductive layer formed over the semiconductor substrate. A diffusion barrier layer is formed over the doped conductive layer. The diffusion barrier layer may be formed from an amorphous semiconductor material. An ohmic contact layer is formed over the diffusion barrier layer. A metal barrier layer is formed over the ohmic contact layer. A metal layer is formed over the metal barrier layer.

Abstract: In a method of forming a semiconductor device, and a semiconductor device formed according to the method, an insulating layer is provided on an underlying contact region of the semiconductor device. An opening is formed in the insulating layer to expose the underlying contact region. A seed layer is provided on sidewalls and a bottom of the opening, the seed layer comprising cobalt. A barrier layer of conductive material is provided in a lower portion of the opening, the seed layer being exposed on sidewalls of an upper portion of the opening. A metal layer is provided on the barrier layer in the opening to form an interlayer contact, the metal layer contacting the seed layer at the sidewalls of the upper portion of the opening.