Patents by Inventor Jang-Ho Park

Jang-Ho Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140159246
    Abstract: A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction
    Type: Application
    Filed: February 18, 2014
    Publication date: June 12, 2014
    Inventors: Jang-ho Park, Jae-kwan Park, Dong-hwa Kwak, So-wi Jin, Byung-jun Hwang, Nam-su Lim
  • Patent number: 8739367
    Abstract: In accordance with the disclosure, in various door constructions, a projection of a door leaf is inserted in a hollow of a doorframe, height of the door leaf is minutely adjusted, and an interval between the door leaf and the doorframe is adjusted, which results in easy fastening of the door leaf and the doorframe and reduced construction time. In addition, the door leaf is completely fastened to the doorframe through the locking mechanism, the door leaf is prevented from being twisted in long use, thereby increasing its durability.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: June 3, 2014
    Inventor: Jang-Ho Park
  • Publication number: 20140124341
    Abstract: Disclosed herein is a touch panel including: a transparent substrate; and a bezel part including a white layer formed at one-side edge of the transparent substrate and a light-shielding layer formed on the white layer, wherein the bezel part has a narrow width and a thin thickness, thereby implementing a display screen larger than that of the other touch panels having the same exterior size and providing the touch panel including the white-colored bezel part having a thin thickness and a uniform and sufficient color.
    Type: Application
    Filed: December 31, 2012
    Publication date: May 8, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Jang Ho Park
  • Patent number: 8698593
    Abstract: There is provided a chip resistor including a ceramic substrate; a first resistance layer formed on the ceramic substrate and including a first conductive metal and a first glass; and a second resistance layer formed on the first resistance layer, including a second conductive metal and a second glass, and having a smaller content of glass than the first resistance layer, thereby obtaining relatively low resistance and a relatively small temperature coefficient of resistance (TCR).
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: April 15, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jang Ho Park, Young Key Kim, Ki Won Suh, Jang Seok Yun, Jin Man Han, Sung Jun Kim
  • Publication number: 20140083827
    Abstract: Disclosed herein is a touch panel including an electrode pattern configured of a combination of unit patterns in which a hole is formed at an intersection region between sides.
    Type: Application
    Filed: December 7, 2012
    Publication date: March 27, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sang Hwan Oh, Jin Uk Lee, Ho Joon Park, Jang Ho Park
  • Publication number: 20140083750
    Abstract: Disclosed herein are a raw glass plate for manufacturing a touch panel and a method of manufacturing a touch panel using the raw glass plate. The raw glass plate includes a unit substrate region divided into an active region and a non-active region that is an edge portion of the active region; electrodes formed on the active region of the unit substrate region; wirings that are formed on the non-active region of the unit substrate region and are electrically connected to the electrodes; and a guard line that is formed outside a position at which the wirings are formed, on the non-active region of the unit substrate region in a longitudinal direction of the wirings.
    Type: Application
    Filed: December 17, 2012
    Publication date: March 27, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Kyoung Soo Chae, In Hyun Jang, Seul Gi Kim, Yun Ki Hong, Seung Joo Shin, Jang Ho Park
  • Patent number: 8673782
    Abstract: A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang-ho Park, Jae-kwan Park, Dong-hwa Kwak, So-wi Jin, Byung-jun Hwang, Nam-su Lim
  • Publication number: 20140069692
    Abstract: Disclosed herein is a touch panel including a transparent substrate and an electrode formed on the transparent substrate and an electrode having light transmittance of 5 to 50%, wherein as the electrode has high light transmittance, such that it is possible to solve a defective problem of visibility of the touch panel due to the opacity and specular phenomenon of the electrode.
    Type: Application
    Filed: November 29, 2012
    Publication date: March 13, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jang Ho Park, Seul Gi Kim, Jin UK Lee, In Hyun Jang, Nam Keun Oh
  • Publication number: 20140048315
    Abstract: Disclosed herein is a touch panel including: a transparent substrate; conductive patterns formed on the transparent substrate such that wavy lines thereof are spaced apart from each other and arranged in parallel with each other, each of the wavy lines having a sine wave form where first peaks and second peaks alternately continue along a length direction thereof; and connecting patterns formed on the transparent substrate, each of the connecting patterns electrically connecting between the wave lines, so that good visibility can be achieved even though electrodes and wirings are disposed in an active area of the transparent substrate, by forming uniform pattern of electrodes and wirings on the transparent substrate.
    Type: Application
    Filed: January 9, 2013
    Publication date: February 20, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Kyoung Soo Chae, Yun Ki Hong, Sang Hwan Oh, Jang Ho Park, Seung Joo Shin, Ho Joon Park
  • Patent number: 8569936
    Abstract: There are provided a piezoelectric resonator and an electrode structure thereof. The piezoelectric resonator includes: a piezoelectric body oscillated according to an electrical signal; and first and second electrodes each including first and second electrode layers stacked on respective both surfaces of the piezoelectric body, wherein the first electrode layer includes one or more selected from the group consisting of chromium (Cr), nickel (Ni), titanium (Ti), and an alloy including any one thereof, the ratio of the thickness of the first electrode layer to the thickness of the first or second electrode is 3% to 30%; and the second electrode layer includes copper (Cu) or an alloy including copper (Cu), and the ratio of the thickness of the second electrode layer to the thickness of the first or second electrode is 70% to 97%.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: October 29, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Jang Ho Park
  • Publication number: 20130154790
    Abstract: There is provided a chip resistor including a ceramic substrate; a first resistance layer formed on the ceramic substrate and including a first conductive metal and a first glass; and a second resistance layer formed on the first resistance layer, including a second conductive metal and a second glass, and having a smaller content of glass than the first resistance layer, thereby obtaining relatively low resistance and a relatively small temperature coefficient of resistance (TCR).
    Type: Application
    Filed: April 6, 2012
    Publication date: June 20, 2013
    Inventors: Jang Ho Park, Young Key Kim, Ki Won Suh, Jang Seok Yun, Jin Man Han, Sung Jun Kim
  • Publication number: 20130102151
    Abstract: A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction
    Type: Application
    Filed: December 10, 2012
    Publication date: April 25, 2013
    Inventors: Jang-ho Park, Jae-kwan Park, Dong-hwa Kwak, So-wi Jin, Byung-jun Hwang, Nam-su Lim
  • Publication number: 20130014345
    Abstract: According to the present invention, in various door constructions, a projection of a door leaf can be easily inserted in a hollow of a doorframe, height of the door leaf can be minutely adjusted, and an interval between the door leaf and the doorframe can be easily adjusted, which can result in easy fastening of the door leaf and the doorframe and reduced construction time. In addition, since the door leaf can be completely fastened to the doorframe through the locking mechanism, the door leaf can be prevented from being twisted in long use, thereby increasing its durability.
    Type: Application
    Filed: March 22, 2011
    Publication date: January 17, 2013
    Inventor: Jang-Ho Park
  • Patent number: 8339859
    Abstract: A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: December 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang-ho Park, Jae-kwan Park, Dong-hwa Kwak, So-wi Jin, Byung-jun Hwang, Nam-su Lim
  • Patent number: 8284016
    Abstract: The present invention provides an array type chip resistor including: a substrate having a plurality of grooves formed on both sides thereof at equal spaces; lower electrodes formed on both sides of a bottom surface of the substrate; upper electrodes formed on both sides of a top surface of the substrate; side electrodes electrically connected to the upper and lower electrodes; a resistive element interposed between lower electrodes of the bottom surface of the substrate; a protection layer covered on the resistive element, the protection layer having both sides which cover a part of the lower electrodes and the resistive element; leveling electrodes being in contact with the lower electrodes exposed to outside of the protection layer; and a plating layer formed on the leveling electrodes.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: October 9, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Heung Bok Ryu, Jang Ho Park, Young Key Kim, Ki Won Suh, Yun Gab Choi
  • Patent number: 8222798
    Abstract: There are provided an electrode structure of a piezoelectric resonator and a piezoelectric resonator including the same. The piezoelectric resonator includes: a piezoelectric plate vibrated by an electrical signal; and first and second electrodes having first to fourth layers stacked on both surfaces thereof, wherein the first and third layers are made of at least one selected from the group consisting of Ti, Ni, Cr, an alloy including Ti and an alloy including Cr and the second and fourth layers are made of Ag or an alloy including Ag.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: July 17, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jong Beom Jeon, Katsushi Yasuda, Jong Pil Lee, Jang Ho Park
  • Patent number: 8213231
    Abstract: A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: July 3, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang-ho Park, Jae-kwan Park, Dong-hwa Kwak, So-wi Jin, Byung-jun Hwang, Nam-su Lim
  • Publication number: 20120147674
    Abstract: A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction
    Type: Application
    Filed: February 24, 2012
    Publication date: June 14, 2012
    Inventors: Jang-ho Park, Jae-kwan Park, Dong-hwa Kwak, So-wi Jin, Byung-jun Hwang, Nam-su Lim
  • Patent number: 8179226
    Abstract: The present invention provides an array type chip resistor including: a substrate formed in a rectangular parallelepiped shape; lower electrodes disposed on both sides of a bottom surface of the substrate at equal spaces; side electrodes extended from some of lower electrodes, formed on outermost edges of both sides of the substrate, in all lower electrodes, to a side surface of the substrate; a resistive element interposed between lower electrodes of the bottom surface of the substrate; a protection layer covered on the resistive element, the protection layer having both sides which cover a part of the lower electrodes and the resistive element; leveling electrodes being in contact with the lower electrodes exposed to outside of the protection layer; and a plating layer formed on the leveling electrodes.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: May 15, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Heung Bok Ryu, Jang Ho Park, Young Key Kim, Ki Won Suh, Yun Gab Choi
  • Publication number: 20110316392
    Abstract: There are provided an electrode structure of a piezoelectric resonator and a piezoelectric resonator including the same. The piezoelectric resonator includes: a piezoelectric plate vibrated by an electrical signal; and first and second electrodes having first to fourth layers stacked on both surfaces thereof, wherein the first and third layers are made of at least one selected from the group consisting of Ti, Ni, Cr, an alloy including Ti and an alloy including Cr and the second and fourth layers are made of Ag or an alloy including Ag.
    Type: Application
    Filed: September 1, 2011
    Publication date: December 29, 2011
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jong Beom JEON, Katsushi YASUDA, Jong Pil LEE, Jang Ho PARK