Abstract: The present invention relates to a method for preparing induced dopaminergic neuronal progenitors (iDPs) comprising inducing an expression of Oct4, Sox2, Klf4, and c-Myc genes in adult cells and direct reprogramming of the adult cells to the iDPs by treating the cells with sonic hedgehog (SHH) and fibroblast growth factor 8 (FGF8); and a cell therapy product and a composition for treating or preventing Parkinson's Disease (PD) which comprises the iDPs as active ingredients. In addition to this, the present invention relates to a method for preparing midbrain dopaminergic neurons comprising isolating NSC-like colony by culturing the iDPs, dissociating the isolated NSC-like colony, and culturing the cells on the neural cell differentiation medium. Further, the present invention relates to a method for treating PD or a method for screening medicine for preventing or treating PD using the cells of the present invention.

Abstract: A memory system including non-volatile memory devices and a corresponding refresh method are disclosed. The method groups memory blocks of the non-volatile memory devices into memory groups, determines a refresh sequence for the memory groups, and refreshes the memory groups in accordance with the refresh sequence.

Abstract: A memory system including non-volatile memory devices and a corresponding refresh method are disclosed. The method groups memory blocks of the non-volatile memory devices into memory groups, determines a refresh sequence for the memory groups, and refreshes the memory groups in accordance with the refresh sequence.

Abstract: A dual inverter system to drive a motor in an electronic apparatus and a method of controlling the same include a first inverter connected to one side of a stator winding of the motor to modulate a pulse width and to adjust power supplied to the motor, a second inverter connected to the other side of the stator winding of the motor to modulate a pulse width and to adjust power supplied to the motor, a first current detector connected to the first inverter to detect a current flowing in the first inverter, a second current detector connected to the second inverter to detect a current flowing in the second inverter, and a controller to control the motor by controlling a pulse-width modulation (PWM) signal applied to the first inverter or the second inverter based on the current flowing in at least one of the first inverter and the second inverter.

Abstract: The present invention relates to display devices, and more particularly to an optical sensing frame in which an infrared sensor module is fastened to a case top with a bracket to secure an assembly margin and prevent the infrared sensor module from mismatching with a liquid crystal display module by relative movement; and a display device therewith, the optical sensing frame includes a case top having a frame shaped upper side, and sides bent and extended from four sides of the upper side perpendicular thereto, first to third brackets fastened to an inside of the upper side of the case top at three corners thereof respectively, and an infrared sensor module placed in each of the first to third brackets.

Abstract: A system for controlling fault tolerance may include a first controller connected to a driver, a first switch connected in parallel to the first controller, a first capacitor connected in parallel to the first switch, a second switch connected in parallel to the first capacitor and different from the first switch, a first power supply connected in parallel to the first capacitor and connected in series to the second switch, and a second capacitor connected to the first switch and a ground of the first power supply and different from the first capacitor. When the first controller is broken down, the second switch may be turned off to interrupt power supply from the first power supply, and the first switch may be turned on to discharge electric charges charged in the second capacitor.

Abstract: A dual inverter system to drive a motor in an electronic apparatus and a method of controlling the same include a first inverter connected to one side of a stator winding of the motor to modulate a pulse width and to adjust power supplied to the motor, a second inverter connected to the other side of the stator winding of the motor to modulate a pulse width and to adjust power supplied to the motor, a first current detector connected to the first inverter to detect a current flowing in the first inverter, a second current detector connected to the second inverter to detect a current flowing in the second inverter, and a controller to control the motor by controlling a pulse-width modulation (PWM) signal applied to the first inverter or the second inverter based on the current flowing in at least one of the first inverter and the second inverter.

Abstract: A sensorless control apparatus of a motor may include: a position estimator configured to compensate for a resistance and a magnetic flux of a permanent magnet of the motor according to a temperature of the motor, and/or configured to generate an estimated speed of a rotor of the motor based on the compensated resistance and the compensated magnetic flux of the permanent magnet; and/or a speed controller configured to generate a command current based on a command speed of the rotor and the estimated speed of the rotor.

Abstract: A memory system including non-volatile memory devices and a corresponding refresh method are disclosed. The method groups memory blocks of the non-volatile memory devices into memory groups, determines a refresh sequence for the memory groups, and refreshes the memory groups in accordance with the refresh sequence.

Abstract: A test system including a test device configured to transmit an input signal and a control signal to at least one complementary metal-oxide semiconductor (CMOS) image sensor via a probe card, and an interface board configured to map the probe card and the test device. The interface board includes an output receiver configured to receive an image signal from the at least one CMOS image sensor and transform the image signal into image data.

Abstract: A memory system including non-volatile memory devices and a corresponding refresh method are disclosed. The method groups memory blocks of the non-volatile memory devices into memory groups, determines a refresh sequence for the memory groups, and refreshes the memory groups in accordance with the refresh sequence.

Abstract: A memory device detects and correct bit errors. The memory device includes cyclic redundancy check (CRC) and error correction code (ECC) circuits. The CRC circuit generates a write CRC code corresponding to data to be stored in memory cells. The ECC circuit generates an ECC code corresponding to the data and detecting and correcting a bit error of the data by means of the ECC code during a read operation. The CRC circuit generates a read CRC code corresponding to data corrected by the ECC circuit during the read operation, and detects a bit error of the data according to a comparison of the read CRC code and the write CRC code.

Abstract: A phase current prediction method is disclosed. The phase current prediction method predicts current representative of a PWM period using a motor model which receives current measured through a single current sensor as an input, instead of the measured current, and determines the predicted current to be phase current.

Abstract: A data storage device comprises a plurality of memory devices, a buffer memory, and a controller. The plurality of memory devices are connected to a plurality of channels and a plurality of ways. The buffer memory temporarily stores data to be written in the memory devices. The controller stores the data in the buffer memory based on channel and way information of the memory devices.

Abstract: A data processing system includes a host and a data processing device configured to store data output from the host. The data processing device includes a compressor configured to compress the data and sort compressed data according to a size of the compressed data and a buffer block configured to store the compressed data that has been sorted.

Abstract: The present invention relates to display devices, and more particularly to an optical sensing frame in which an infrared sensor module is fastened to a case top with a bracket to secure an assembly margin and prevent the infrared sensor module from mismatching with a liquid crystal display module by relative movement; and a display device therewith, the optical sensing frame includes a case top having a frame shaped upper side, and sides bent and extended from four sides of the upper side perpendicular thereto, first to third brackets fastened to an inside of the upper side of the case top at three corners thereof respectively, and an infrared sensor module placed in each of the first to third brackets.

Abstract: A memory device includes a control module to determine first data blocks needing a garbage collection, to determine second data blocks needing memory refresh among the determined first data blocks, and to execute the garbage collection first on the second data blocks.

Abstract: A memory system including non-volatile memory devices and a corresponding refresh method are disclosed. The method groups memory blocks of the non-volatile memory devices into memory groups, determines a refresh sequence for the memory groups, and refreshes the memory groups in accordance with the refresh sequence.

Abstract: A circuit for stabilizing a common voltage of a liquid crystal display device includes a data driving unit for providing video data to a liquid crystal display panel and a gate driving unit for providing scan pulses to the liquid crystal display panel, a timing controller for outputting various control signals for controlling the data driving unit and the gate driving unit, and outputting the video data, and a common voltage output unit for controlling outputting of a common voltage provided to the liquid crystal display panel according to a gate output enable signal inputted from the timing controller to thereby minimize the common voltage from being unstable.

Abstract: A method is for recovering a block mapping table in a system including a flash memory device, where the block mapping table utilizes address mapping in accordance with a wear-leveling scheme. The method includes reading block arrangement information from the flash memory device for the wear-leveling scheme, restoring the block mapping table with reference to allocation block information included in the block arrangement information and scanning address allocation information included in spare regions of erased blocks of the flash memory device with reference to erased block information included in the block arrangement information and updating the block mapping table in accordance with the scanned address allocation information.