Abstract: A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.

Abstract: The stacked semiconductor device including a first chip, a second chip positioned on the first chip, the second chip being connected to a plurality of first penetration electrodes and including a first memory and a memory controller that are each controlled by the first chip, and a second memory positioned on the second chip and connected to a plurality of second penetration electrodes and controlled by the memory controller.

Abstract: The semiconductor device is provided. The semiconductor device includes a substrate, an electrostatic discharge layer disposed on the substrate and including a plurality of electrostatic discharge circuits, at least one semiconductor chip stacked on the electrostatic discharge layer, and a plurality of vertical electrical connections which pass through the at least one semiconductor chip and the electrostatic discharge layer to connect the at least one semiconductor chip to the semiconductor substrate. The vertical electrical connections are connected to the electrostatic discharge circuits, respectively.

Abstract: A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.

Abstract: A semiconductor memory device comprises a memory cell array comprising a plurality of memory cells, and a filling command determiner that receives a command signal and an address signal and determines whether the command signal corresponds to a filling command. Upon determining that the command signal corresponds to a filling command, the filling command determiner connects a first source voltage to a bitline and connects a second source voltage to a complementary bitline corresponding to the bitline. The bitline is connected to a selected memory cell corresponding to the address signal.

Abstract: A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.

Abstract: In one embodiment, a method of performing data training in a system including a memory controller and at least a first memory device including a group of memory banks is disclosed. The method includes providing a plurality of enabling states for the group of memory banks, wherein each enabling state is different and for each enabling state a set of the memory banks of the group is enabled and any remaining of the memory banks of the group are not enabled. The method further includes performing a first data training procedure that includes a series of first data training operations for the first memory device, each data training operation being performed for a different one of the plurality of enabling states, generating a noise profile based on the series of first data training operations, statistically analyzing the noise profile to select a reference enabling state of the group of memory banks, and performing a second data training procedure for the first memory device using the reference enabling state.

Abstract: A semiconductor memory device comprises a memory cell array comprising a plurality of memory banks. The semiconductor memory device performs refresh operations on the memory cell array using a normal refresh operation mode and a self-refresh operation mode. In the normal refresh operation mode, the semiconductor memory device performs refresh operations using an external high power supply voltage, and in the self-refresh operation mode, the semiconductor memory device performs refresh operations using an internal high power supply voltage. In the self-refresh operation mode, the refresh operations are performed in units of memory banks or memory bank groups.

Abstract: A memory controller includes a memory capacity setting circuit and an address selecting circuit. The memory capacity setting circuit is configured to set a valid memory capacity of a memory device based on a defective cell information signal, and generate a valid memory capacity signal based on the valid memory capacity. The address selecting circuit is configured to disable an address signal corresponding to a memory block having a defective cell, and generate a selection address signal based on the valid memory capacity signal and the disabled address signal. A non-defective cell in a memory cell array is activated based on the selection address signal and a command signal.

Abstract: A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.

Abstract: Provided are a control signal generation circuit and a method for generating a control signal controlled in units of bit time of a clock signal. The control signal generation circuit includes an input terminal, a first output terminal, and a second output terminal. The control signal generation circuit receives an input signal inputted to the input terminal in response to a clock signal and outputs a column latch signal and a data input/output command signal, which are separately activated and have a first time interval therebetween, to the first input terminal and the second input terminal, respectively, each in response to a test enable signal at a first state, or outputs the column latch signal and the data input/output command signal, which are separately activated and have a second time interval therebetween, to the first output terminal and the second output terminal, respectively, each in response to a test enable signal at a second state.

Abstract: A semiconductor memory device having a mesh-type structure of a precharge voltage line is provided. The semiconductor memory device includes a plurality of memory cell arrays, a plurality of bit line precharge circuit units, and a first precharge voltage line and a second precharge voltage line. Each of the plurality of memory cell arrays include a plurality of memory cells and a plurality of bit line pairs for outputting and receiving data to and from each of the memory cells and are arranged in a matrix. The plurality of bit line precharge circuit units precharge and equalize corresponding bit line pairs of the memory cell arrays into predetermined precharge voltages. The first precharge voltage line and the second precharge voltage line are arranged in a mesh in each region between the plurality of memory cell arrays.

Abstract: A semiconductor memory device having a mesh-type structure of a precharge voltage line is provided. The semiconductor memory device includes a plurality of memory cell arrays, a plurality of bit line precharge circuit units, and a first precharge voltage line and a second precharge voltage line. Each of the plurality of memory cell arrays include a plurality of memory cells and a plurality of bit line pairs for outputting and receiving data to and from each of the memory cells and are arranged in a matrix. The plurality of bit line precharge circuit units precharge and equalize corresponding bit line pairs of the memory cell arrays into predetermined precharge voltages. The first precharge voltage line and the second precharge voltage line are arranged in a mesh in each region between the plurality of memory cell arrays.