Patents by Inventor Jang Won Kim
Jang Won Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240127627Abstract: Disclosed herein is an apparatus and method for detecting an emotional change through facial expression analysis. The apparatus for detecting an emotional change through facial expression analysis includes a memory having at least one program recorded thereon, and a processor configured to execute the program, wherein the program includes a camera image acquisition unit configured to acquire a moving image including at least one person, a preprocessing unit configured to extract a face image of a user from the moving image and preprocess the extracted face image, a facial expression analysis unit configured to extract a facial expression vector from the face image of the user and cumulatively store the facial expression vector, and an emotional change analysis unit configured to detect a temporal location of a sudden emotional change by analyzing an emotion signal extracted based on cumulatively stored facial expression vector values.Type: ApplicationFiled: October 11, 2023Publication date: April 18, 2024Inventors: Byung-Ok HAN, Ho-Won KIM, Jang-Hee YOO, Cheol-Hwan YOO, Jae-Yoon JANG
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Patent number: 11955271Abstract: A radio frequency (RF) weak magnetic field detection sensor includes a ferromagnetic core, a pickup coil disposed to surround the ferromagnetic core, a substrate that includes an opening, a core pad connected to the ferromagnetic core and a coil pad connected to the pickup coil, and an insulating tube interposed between the ferromagnetic core and the pickup coil. The insulating tube includes a bobbin around which the pickup coil is wound, and a core hole formed to pass through the bobbin and configured to accommodate the ferromagnetic core.Type: GrantFiled: May 23, 2023Date of Patent: April 9, 2024Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Jang Yeol Kim, In Kui Cho, Hyunjoon Lee, Sang-Won Kim, Seong-Min Kim, Jung Ick Moon, Woo Cheon Park, Je Hoon Yun, Jaewoo Lee, Ho Jin Lee, Dong Won Jang, Kibeom Kim, Seungyoung Ahn
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Patent number: 11916309Abstract: An apparatus and method for transmitting and receiving magnetic field signals in a magnetic field communication system are provided. The apparatus includes a controller configured to generate a communication signal, matching units that are configured to receive the communication signal and that respectively correspond to different matching frequencies, and loop antennas that are connected to the matching units, respectively, and that are configured to convert communication signals according to the different matching frequencies into magnetic transmission signals in the form of magnetic field energy and to transmit the magnetic transmission signals.Type: GrantFiled: December 15, 2020Date of Patent: February 27, 2024Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jaewoo Lee, In Kui Cho, Sang-Won Kim, Seong-Min Kim, Ho Jin Lee, Jang Yeol Kim, Jung Ick Moon, Woo Cheon Park, Je Hoon Yun, Hyunjoon Lee, Dong Won Jang
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Patent number: 11894360Abstract: A semiconductor device includes a slit pattern and a trench pattern disposed to extend substantially in parallel with each other in a first direction and channel plugs between the slit pattern and the trench pattern. The channel plugs include a first channel plug adjacent to the slit pattern. A top surface shape of the first channel plug is an elliptical shape. A long axis direction of the first channel plug and the first direction form an acute angle.Type: GrantFiled: August 19, 2021Date of Patent: February 6, 2024Assignee: SK hynix Inc.Inventor: Jang Won Kim
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Patent number: 11823999Abstract: The present technology relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another, a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack, a plurality of channel plugs vertically formed through the first stack and the second stack, and at least one dummy plug vertically formed through the second without passing through the first stack.Type: GrantFiled: October 1, 2021Date of Patent: November 21, 2023Assignee: SK hynix Inc.Inventors: Hae Chan Park, Jang Won Kim, Jae Taek Kim
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Publication number: 20230126213Abstract: The present technology includes a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a first stack structure over a lower structure in which a cell region and a slimming region are defined, including a plurality of first gate lines, a first interlayer insulating structure over the first stack structure, a second stack structure over the first interlayer insulating structure, and a plurality of vertical plugs passing through the first stack structure, the first interlayer insulating structure and the second stack structure in the cell region.Type: ApplicationFiled: May 26, 2022Publication date: April 27, 2023Applicant: SK hynix Inc.Inventors: Won Geun CHOI, Jang Won KIM, Jung Shik JANG
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Publication number: 20220399364Abstract: A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a gate stacked structure with a cell array region and a contact region with a stepped shape, and a roughness of a first sidewall of the cell array region is greater than that of a second sidewall of the contact region.Type: ApplicationFiled: November 30, 2021Publication date: December 15, 2022Applicant: SK hynix Inc.Inventors: Jang Won KIM, Mi Seong PARK, In Su PARK, Jung Shik JANG, Won Geun CHOI
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Publication number: 20220344366Abstract: A semiconductor device includes a gate structure including conductive layers and insulating layers alternately stacked with each other, channel structures passing through the gate structure and arranged in a first direction, a cutting structure extending in the first direction and passing through the channel structures, and a first slit structure passing through the gate structure and extending in a second direction crossing the first direction.Type: ApplicationFiled: September 23, 2021Publication date: October 27, 2022Applicant: SK hynix Inc.Inventors: Mi Seong PARK, Jang Won KIM, In Su PARK, Jung Shik JANG, Won Geun CHOI, Jung Dal CHOI
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Publication number: 20220336437Abstract: A semiconductor device includes a slit pattern and a trench pattern disposed to extend substantially in parallel with each other in a first direction and channel plugs between the slit pattern and the trench pattern. The channel plugs include a first channel plug adjacent to the slit pattern. A top surface shape of the first channel plug is an elliptical shape. A long axis direction of the first channel plug and the first direction form an acute angle.Type: ApplicationFiled: August 19, 2021Publication date: October 20, 2022Applicant: SK hynix Inc.Inventor: Jang Won KIM
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Publication number: 20220271055Abstract: There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a first gate stack structure and a second gate stack structure, disposed on a substrate; and a slit disposed between the first gate stack structure and the second gate stack structure to electrically isolate the first gate stack structure and the second gate stack structure from each other.Type: ApplicationFiled: August 11, 2021Publication date: August 25, 2022Applicant: SK hynix Inc.Inventors: Won Geun CHOI, Jung Shik JANG, Jang Won KIM, Mi Seong PARK
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Publication number: 20220238347Abstract: A method for fabricating a semiconductor includes: forming an etch target layer on a substrate, wherein the etch target layer includes an alternating stack layer and a sacrificial stack layer on the alternating stack layer, and wherein the sacrificial stack layer includes the same material as the alternating stack layer; forming a hard mask pattern on the sacrificial stack layer; etching the etch target layer using the hard mask pattern as an etch barrier to form a plurality of initial high aspect ratio features, the initial high aspect ratio features penetrating through the etch target layer; and removing the hard mask pattern and the sacrificial stack layer to form a plurality of high aspect ratio features.Type: ApplicationFiled: July 14, 2021Publication date: July 28, 2022Applicant: SK hynix Inc.Inventor: Jang Won KIM
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Publication number: 20220020686Abstract: The present technology relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another, a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack, a plurality of channel plugs vertically formed through the first stack and the second stack, and at least one dummy plug vertically formed through the second without passing through the first stack.Type: ApplicationFiled: October 1, 2021Publication date: January 20, 2022Applicant: SK hynix Inc.Inventors: Hae Chan PARK, Jang Won KIM, Jae Taek KIM
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Patent number: 11145594Abstract: The present technology relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another, a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack, a plurality of channel plugs vertically formed through the first stack and the second stack, and at least one dummy plug vertically formed through the second without passing through the first stack.Type: GrantFiled: November 26, 2019Date of Patent: October 12, 2021Assignee: SK hynix Inc.Inventors: Hae Chan Park, Jang Won Kim, Jae Taek Kim
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Publication number: 20210028105Abstract: The present technology relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another, a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack, a plurality of channel plugs vertically formed through the first stack and the second stack, and at least one dummy plug vertically formed through the second without passing through the first stack.Type: ApplicationFiled: November 26, 2019Publication date: January 28, 2021Applicant: SK hynix Inc.Inventors: Hae Chan PARK, Jang Won KIM, Jae Taek KIM
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Patent number: 10734407Abstract: A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.Type: GrantFiled: June 21, 2019Date of Patent: August 4, 2020Assignee: SK hynix Inc.Inventors: Hae Chan Park, Jang Won Kim, Gong Hyun Sa
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Publication number: 20190312057Abstract: A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.Type: ApplicationFiled: June 21, 2019Publication date: October 10, 2019Applicant: SK hynix Inc.Inventors: Hae Chan PARK, Jang Won KIM, Gong Hyun SA
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Patent number: 10373971Abstract: A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.Type: GrantFiled: April 14, 2017Date of Patent: August 6, 2019Assignee: SK hynix Inc.Inventors: Hae Chan Park, Jang Won Kim, Gong Hyun Sa
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Publication number: 20180053779Abstract: A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.Type: ApplicationFiled: April 14, 2017Publication date: February 22, 2018Applicant: SK hynix Inc.Inventors: Hae Chan PARK, Jang Won KIM, Gong Hyun SA
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Patent number: D799018Type: GrantFiled: May 12, 2016Date of Patent: October 3, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jang-Won Kim, Jun-Kyo Lee
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Patent number: D958850Type: GrantFiled: November 25, 2020Date of Patent: July 26, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jang-Won Kim, Ae-Ryun Kim, Seok-Woo Kim, Sang-Hyun Lee, Young-Sun Shin, Kang-Doo Kim, Dong-Hyuk Uim