Patents by Inventor Janice Adams

Janice Adams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070061764
    Abstract: Keyword-based verification of proper connectivity of a circuit design including a plurality of cells is disclosed. In one embodiment, a method includes assigning a keyword to each relevant pin of the circuit design, the keyword indicates a verification rule for a domain starting at the relevant pin; tracing the domain starting at the relevant pin, including recording a circuit instance identifier of each cell encountered to generate a traced circuit instance set; and verifying proper connectivity using the verification rule and the traced circuit instance set. The keyword may also indicate a name that drives the creation of a domain, or a trace rule that instructs the tracing. If the traced circuit instance sets do not match the pre-defined relationships, the verification fails and the user is notified that the logic must be modified. The keyword-based verification can occur between domains of the same circuit or a traced circuit instance set can be compared to an expected set.
    Type: Application
    Filed: September 15, 2005
    Publication date: March 15, 2007
    Applicant: INTERNTIONAL BUSINESS MACHINES CORPORATION
    Inventors: Janice Adams, Michael Ouellette, Bruce Raymond
  • Publication number: 20070047343
    Abstract: A method and system for repairing defective memory in a semiconductor chip. The chip has memory locations, redundant memory, and a central location for ordered fuses. The ordered fuses identify in compressed format defective sections of the memory locations. The defective sections are replaceable by sections of the redundant memory. The ordered fuses have an associated a fuse bit pattern of bits which sequentially represents the defective sections in the compressed format. The method and system determines the order in which the memory locations are wired together; designs a shift register of latches through the memory locations in accordance with the order in which the memory locations are wired together; and associates each of the latches with a corresponding bit of an uncompressed bit pattern from which the fuse bit pattern is derived. The uncompressed bit pattern comprises a sequence of bits, representing the defective sections in uncompressed format.
    Type: Application
    Filed: October 24, 2006
    Publication date: March 1, 2007
    Inventors: Janice Adams, Frank Distler, Mark Ollive, Michael Ouellette, Jeannie Panner
  • Patent number: 4739809
    Abstract: A handbag is disclosed which is essentially rectangular with a large central compartment having a top opening. Shallow internal compartments are spaced around the periphery of the opening to hold small items for easy access through the opening. In addition, flat external compartments with slots and flap closures are provided for sheet material which sheet material may be retrieved through the slots in single fashion.
    Type: Grant
    Filed: June 4, 1986
    Date of Patent: April 26, 1988
    Inventor: Janice Adams