Patents by Inventor Janusz Balicki

Janusz Balicki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly
    Patent number: 5970255
    Abstract: A programmable input/output device for use with a programmable logic device (PLD) is presented comprising an input buffer, an output buffer and programmable elements. The programmable elements may be programmed to select a logic standard for the input/output device to operate at. For instance, a given set of Select Bits applied to the programmable elements may select TTL logic, in which case the input and output buffers would operate according to the voltage levels appropriate for TTL logic (e.g., 0.4 volts to 2.4 volts). For a different set of Select Bits, the GTL logic standard would be applied (e.g., 0.8 volts to 1.2 volts). The invention enables a single PLD to be used in conjunction with various types of external circuitry.
    Type: Grant
    Filed: October 16, 1995
    Date of Patent: October 19, 1999
    Assignee: Altera Corporation
    Inventors: Nghia Tran, Ying Xuan Li, Janusz Balicki, John Costello
  • System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly
    Patent number: RE40011
    Abstract: A programmable input/output device for use with a programmable logic device (PLD) is presented comprising an input buffer, an output buffer and programmable elements. The programmable elements may be programmed to select a logic standard for the input/output device to operate at. For instance, a given set of Select Bits applied to the programmable elements may select TTL logic, in which case the input and output buffers would operate according to the voltage levels appropriate for TTL logic (e.g., 0.4 volts to 2.4 volts). For a different set of Select Bits, the GTL logic standard would be applied (e.g., 0.8 volts to 1.2 volts). The invention enables a single PLD to be used in conjunction with various types of external circuitry.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: January 22, 2008
    Assignee: Altera Corporation
    Inventors: Nghia Tran, Ying Xuan Li, Janusz Balicki, John Costello