Patents by Inventor Jared E. Bendt

Jared E. Bendt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for efficient store/restore of state information during a power state transition
    Patent number: 9939885
    Abstract: A processor is described having streamlining circuitry that has a first interface to receive information from a memory describing: i) respective addresses for internal state information of a power domain; ii) respective addresses of a memory where the internal state information is stored when the power domain is powered down; and, iii) meta data for transferring the state information between the power domain and where the internal state information is stored when the power domain is powered down.
    Type: Grant
    Filed: July 3, 2016
    Date of Patent: April 10, 2018
    Assignee: INTEL CORPORATION
    Inventors: Shaun M. Conrad, Jared E. Bendt, Janardhan Lavakumar
  • METHOD AND APPARATUS FOR EFFICIENT STORE/RESTORE OF STATE INFORMATION DURING A POWER STATE TRANSITION
    Publication number: 20160313787
    Abstract: A processor is described having streamlining circuitry that has a first interface to receive information from a memory describing: i) respective addresses for internal state information of a power domain; ii) respective addresses of a memory where the internal state information is stored when the power domain is powered down; and, iii) meta data for transferring the state information between the power domain and where the internal state information is stored when the power domain is powered down.
    Type: Application
    Filed: July 3, 2016
    Publication date: October 27, 2016
    Inventors: SHAUN M. CONRAD, JARED E. BENDT, JANARDHAN LAVAKUMAR
  • Method and apparatus for efficient store/restore of state information during a power state
    Patent number: 9383812
    Abstract: A processor is described having streamlining circuitry that has a first interface to receive information from a memory describing: i) respective addresses for internal state information of a power domain; ii) respective addresses of a memory where the internal state information is stored when the power domain is powered down; and, iii) meta data for transferring the state information between the power domain and where the internal state information is stored when the power domain is powered down.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Shaun M. Conrad, Jared E. Bendt, Janardhan Lavakumar
  • Method, apparatus, and system for energy efficiency and energy conservation including dynamic C0-state cache resizing
    Patent number: 8984311
    Abstract: Embodiments of systems, apparatuses, and methods for energy-efficient operation of a device are described. In some embodiments, a cache performance indicator of a cache is monitored, and a set of one or more cache performance parameters based on the cache performance indicator is determined. The cache is dynamically resized to an optimal cache size based on a comparison of the cache performance parameters to their energy-efficient targets to reduce power consumption.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: March 17, 2015
    Assignee: Intel Corporation
    Inventors: Jaideep Moses, Rameshkumar G. Illikkal, Ravishankar Iyer, Jared E. Bendt, Sadagopan Srinivasan, Andrew J. Herdrich, Ashish V. Choubal, Avinash N. Ananthakrishnan, Vijay S. R. Degalahal
  • Method and Apparatus For Efficient Store/Restore of State Information During A Power State Transition
    Publication number: 20140095910
    Abstract: A processor is described having streamlining circuitry that has a first interface to receive information from a memory describing: i) respective addresses for internal state information of a power domain; ii) respective addresses of a memory where the internal state information is stored when the power domain is powered down; and, iii) meta data for transferring the state information between the power domain and where the internal state information is stored when the power domain is powered down.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Shaun M. Conrad, Jared E. Bendt, Janardhan Lavakumar
  • METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DYNAMIC C0-STATE CACHE RESIZING
    Publication number: 20120173907
    Abstract: Embodiments of systems, apparatuses, and methods for energy-efficient operation of a device are described. In some embodiments, a cache performance indicator of a cache is monitored, and a set of one or more cache performance parameters based on the cache performance indicator is determined. The cache is dynamically resized to an optimal cache size based on a comparison of the cache performance parameters to their energy-efficient targets to reduce power consumption.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 5, 2012
    Inventors: Jaideep MOSES, Rameshkumar G. Illikkal, Ravishankar Iyer, Jared E. Bendt, Sadagopan Srinivasan, Andrew J. Herdrich, Ashish V. Choubal, Avinash N. Ananthakrishnan, Vijay S.R. Degalahal