Patents by Inventor Jared LeVan Zerbe
Jared LeVan Zerbe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230160922Abstract: Individual health related events (e.g., handwashing events) can be detected based on multiple sensors including motion and audio sensors. Detecting a qualifying handwashing event can include detecting a qualifying scrubbing event based on motion data (e.g., accelerometer data) and a qualifying rinsing event based on audio data. In some examples, power consumption can be reduced by implementing one or more power saving mitigations.Type: ApplicationFiled: January 23, 2023Publication date: May 25, 2023Inventors: Gierad LAPUT, Jared LeVan ZERBE, William C. ATHAS, Andreas Edgar SCHOBEL, Shawn R. SCULLY, Brian H. TSANG, Kevin LYNCH, Charles MAALOUF, Shiwen ZHAO
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Patent number: 11639944Abstract: Individual health related events (e.g., handwashing events) can be detected based on multiple sensors including motion and audio sensors. Detecting a qualifying handwashing event can include detecting a qualifying scrubbing event based on motion data (e.g., accelerometer data) and a qualifying rinsing event based on audio data. In some examples, power consumption can be reduced by implementing one or more power saving mitigations.Type: GrantFiled: August 14, 2020Date of Patent: May 2, 2023Assignee: Apple Inc.Inventors: Gierad Laput, Jared LeVan Zerbe, William C. Athas, Andreas Edgar Schobel, Shawn R. Scully, Brian H. Tsang, Kevin Lynch, Charles Maalouf, Shiwen Zhao
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Patent number: 11561239Abstract: Individual health related events (e.g., handwashing events) can be detected based on multiple sensors including motion and audio sensors. Detecting a qualifying handwashing event can include detecting a qualifying scrubbing event based on motion data (e.g., accelerometer data) and a qualifying rinsing event based on audio data. In some examples, power consumption can be reduced by implementing one or more power saving mitigations.Type: GrantFiled: August 14, 2020Date of Patent: January 24, 2023Assignee: Apple Inc.Inventors: Gierad Laput, Jared LeVan Zerbe, William C. Athas, Andreas Edgar Schobel, Shawn R. Scully, Brian H. Tsang, Kevin Lynch, Charles Maalouf, Shiwen Zhao
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Patent number: 11063741Abstract: A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.Type: GrantFiled: October 21, 2019Date of Patent: July 13, 2021Assignee: RAMBUS INC.Inventors: Hae-Chang Lee, Jared LeVan Zerbe, Carl William Werner
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Publication number: 20210063434Abstract: Individual health related events (e.g., handwashing events) can be detected based on multiple sensors including motion and audio sensors. Detecting a qualifying handwashing event can include detecting a qualifying scrubbing event based on motion data (e.g., accelerometer data) and a qualifying rinsing event based on audio data. In some examples, power consumption can be reduced by implementing one or more power saving mitigations.Type: ApplicationFiled: August 14, 2020Publication date: March 4, 2021Inventors: Gierad LAPUT, Jared LeVan ZERBE, William C. ATHAS, Andreas Edgar SCHOBEL, Shawn R. SCULLY, Brian H. TSANG, Kevin LYNCH, Charles MAALOUF, Shiwen ZHAO
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Publication number: 20200162233Abstract: A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.Type: ApplicationFiled: October 21, 2019Publication date: May 21, 2020Inventors: Hae-Chang Lee, Jared LeVan Zerbe, Carl William Werner
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Patent number: 10310999Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.Type: GrantFiled: September 13, 2017Date of Patent: June 4, 2019Inventors: Jared LeVan Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz, Leung Yu, Roxanne Vu, Jun Kim, Bruno W. Garlepp, Tsyr-Chyang Ho, Benedict Chung-Kwong Lau
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Publication number: 20180095916Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.Type: ApplicationFiled: September 13, 2017Publication date: April 5, 2018Inventors: Jared LeVan Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz, Leung Yu, Roxanne Vu, Jun Kim, Bruno W. Garlepp, Tsyr-Chyang Ho, Benedict Chung-Kwong Lau
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Patent number: 9785589Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.Type: GrantFiled: July 29, 2016Date of Patent: October 10, 2017Assignee: Rambus Inc.Inventors: Jared LeVan Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz, Leung Yu, Roxanne Vu, Jun Kim, Bruno W. Garlepp, Tsyr-Chyang Ho, Benedict Chung-Kwong Lau
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Publication number: 20170031854Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.Type: ApplicationFiled: July 29, 2016Publication date: February 2, 2017Inventors: Jared LeVan Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz, Leung Yu, Roxanne Vu, Jun Kim, Bruno W. Garlepp, Tsyr-Chyang Ho, Benedict Chung-Kwong Lau
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Patent number: 9405678Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.Type: GrantFiled: September 21, 2015Date of Patent: August 2, 2016Assignee: Rambus Inc.Inventors: Jared LeVan Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz, Leung Yu, Roxanne Vu, Jun Kim, Bruno W. Garlepp, Tsyr-Chyang Ho, Benedict Chung-Kwong Lau
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Publication number: 20160011973Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.Type: ApplicationFiled: September 21, 2015Publication date: January 14, 2016Inventors: Jared LeVan Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz, Leung Yu, Roxanne Vu, Jun Kim, Bruno W. Garlepp, Tsyr-Chyang Ho, Benedict Chung-Kwong Lau
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Patent number: 9164933Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.Type: GrantFiled: February 3, 2015Date of Patent: October 20, 2015Assignee: Rambus Inc.Inventors: Jared LeVan Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz, Leung Yu, Roxanne Vu, Jun Kim, Bruno W. Garlepp, Tsyr-Chyang Ho, Benedict Chung-Kwong Lau
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Publication number: 20150169478Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.Type: ApplicationFiled: February 3, 2015Publication date: June 18, 2015Inventors: Jared LeVan Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz, Leung Yu, Roxanne Vu, Jun Kim, Bruno W. Garlepp, Tsyr-Chyang Ho, Benedict Chung-Kwong Lau
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Patent number: 8948212Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.Type: GrantFiled: January 13, 2014Date of Patent: February 3, 2015Assignee: Rambus Inc.Inventors: Jared LeVan Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz, Leung Yu, Roxanne Vu, Jun Kim, Bruno W. Garlepp, Tsyr-Chyang Ho, Benedict Chung-Kwong Lau
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Publication number: 20140229667Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.Type: ApplicationFiled: January 13, 2014Publication date: August 14, 2014Applicant: Rambus Inc.Inventors: Jared LeVan Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz, Leung Yu, Roxanne Vu, Jun Kim, Bruno W. Garlepp, Tsyr-Chyang Ho, Benedict Chung-Kwong Lau
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Patent number: 8774337Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.Type: GrantFiled: December 10, 2012Date of Patent: July 8, 2014Assignee: Rambus Inc.Inventors: Hae-Chang Lee, Jared LeVan Zerbe, Carl William Werner
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Patent number: 8630317Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.Type: GrantFiled: April 13, 2012Date of Patent: January 14, 2014Assignee: Rambus Inc.Inventors: Jared LeVan Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz, Leung Yu, Roxanne Vu, Jun Kim, Bruno W. Garlepp, Tsyr-Chyang Ho, Benedict Chung-Kwong Lau
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Patent number: 8610307Abstract: A method of adjusting a voltage supply to an electronic device coupled to a wired communication link in accordance with a performance metric associated with the wired communication link. A voltage adjust signal is generated based on the performance metric. The voltage adjustment signal is then used for updating the voltage supply to the electronic device.Type: GrantFiled: January 22, 2013Date of Patent: December 17, 2013Assignee: Rambus Inc.Inventors: Jared LeVan Zerbe, Jaeha Kim, Yohan U. Frans, Huy M. Nguyen
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Publication number: 20130264871Abstract: A method of adjusting a voltage supply to an electronic device coupled to a wired communication link in accordance with a performance metric associated with the wired communication link. A voltage adjust signal is generated based on the performance metric. The voltage adjustment signal is then used for updating the voltage supply to the electronic device.Type: ApplicationFiled: January 22, 2013Publication date: October 10, 2013Inventors: Jared LeVan Zerbe, Jaeha Kim, Yohan U. Frans, Huy M. Nguyen