Abstract: A technique for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system, wherein the transition-limiting code has a characteristic such that at least one signal level is periodically unused. The method comprises utilizing the at least one periodically unused signal level in a codeword that has been encoded using the transition-limiting code so as to represent additional information in the multi-level signaling system.

Abstract: A technique for determining an optimal transition-limiting code for use in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for determining an optimal transition-limiting code for use in a multi-level signaling system. Such a method comprises determining a coding gain for each of a plurality of transition-limiting codes, and selecting one of the plurality of transition-limiting codes having a largest coding gain for use in the multi-level signaling system.

Abstract: A circuit, apparatus and method for maximizing system margins by adjusting a duty-cycle of a clock signal in a receive circuit to whatever duty-cycle is optimal for the particular incoming serial data, rather than the typical 50% duty-cycle, is provided in embodiments of the present invention. A receive circuit, including duty-cycle-correction logic, is included in a double-data rate communication apparatus having a transmit circuit transmitting serial data having duty-cycle distortion. A receive circuit includes a first and second sampler to obtain data and edge values of an incoming serial data responsive to a data and edge clock, respectively. A duty-cycle-correction logic generates a duty-cycle-correction signal to a duty-cycle clock integrator that adjusts the edge clock signals while maintaining quadrature to the data clocks. In an embodiment of the present invention, a duty-cycle-correction logic includes an evaluator circuit to generate an up or down signal responsive to the data and/or edge values.

Abstract: A circuit, apparatus and method obtains system margin at the receive circuit using phase shifted data sampling clocks while allowing the CDR to remain synchronized with the incoming data stream in embodiments of the present invention. In a first embodiment of the present invention, logic is provided in a CDR unit of a serial receiving circuit by disengaging or freezing the CDR loop during a waveform capture mode. In a second embodiment of the present invention, an additional clock phase adjuster and sampling stage is used to generate offset clock signals independent of CDR tracking clocks. In a third embodiment of the present invention, edge clocks alone are used for CDR tracking of half rate serial data while data clocks are used for capturing a waveform. In a fourth embodiment of the present invention, a predetermined pattern having a single transition is used for CDR tracking.

Abstract: A technique for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system, wherein the transition-limiting code has a characteristic wherein a signal level is periodically unused. Such a method may comprise modifying the transition-limiting code such that the periodically unused signal level is used to represent additional information.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. Evaluation is accomplished using the same circuits actually involved in normal operation of the signaling system. Capability for in-situ testing of a signaling system is provided, and information may be obtained from the actual perspective of a receive circuit in the system. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. Preferably, the patterns are repeating patterns that allow many iterations of testing to be performed. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. Evaluation is accomplished using the same circuits actually involved in normal operation of the signaling system. Capability for in-situ testing of a signaling system is provided, and information may be obtained from the actual perspective of a receive circuit in the system. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. Preferably, the patterns are repeating patterns that allow many iterations of testing to be performed. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns.

Abstract: A system and method are shown for generation of at least one reference voltage level in a bus system. A reference voltage generator on a current driver includes at least one reference voltage level, at least one control signal, and an active device. The active device is coupled to the at least one control signal, such as a current control signal, and a selected reference voltage of the at least one reference voltage level. The active device is arranged to shift the at least one reference voltage level based on the at least one current control signal such as an equalization signal, a crosstalk signal, or the combination thereof, employed on the current driver.