Abstract: Reference generator systems (108, 130) and methods (200) are presented for providing bitline reference voltages for memory access operations in a ferroelectric memory device (102). The reference generator system (108, 130) comprises a primary capacitance (130), a precharge system (132) that charges the primary capacitance, and a reference system (108) with a plurality of local reference circuits (108a) associated with corresponding array columns that individually comprise a staging capacitance (Cs), a first switching device (S1) coupled between the staging capacitance and the primary capacitance (130), and a second switching device (S2, S3) coupled between the staging capacitance (Cs) and a bitline of the corresponding array column.

Abstract: A SRAM cell wherein the pull up load of the cell is inherent ferroelectric leakage. The power down writeback may include boosting the word line. The power down writeback may also include discharging the plate from VDD to ground. Furthermore, the plate is held high during read and write operations.

Abstract: Ferroelectric memory devices and control circuits therefor are presented, in which memory array control and timing signals are derived according to tap outputs from a group of series connected delay elements. Some or all of the individual delay elements comprise one or more trim inputs and a variable delay circuit that provides an output signal a variable delay time after the delay element input signal, where the variable delay is set according to the trim inputs, allowing the control signals to be adjusted or trimmed to accommodate fabrication process variations.

Abstract: Ferroelectric device structures are provided comprising a ferroelectric capacitor, first and second circuit elements, and first and second contacts. The ferroelectric capacitor residing over the first and second circuit elements, and first and second contacts, has a conductive plate that may be used as a local interconnect layer. The conductive plate extends between and electrically couples first and second circuit elements directly through first and second contacts of the ferroelectric memory device. Methods are also provided for forming the local interconnect layer within the conductive plate of the ferroelectric capacitor.

Abstract: An embodiment of the invention is a four transistor SRAM 10 that contains at least one ferroelectric capacitor 20,21.