Abstract: A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. In some embodiments, the cell is only read in response to an event. If, in response to that reading, it is determined that the cell has changed state or resistance, it may deduce whether the change is a result of thermal exposure. Corrective measures may then be taken.

Abstract: A system comprises a redundancy circuit board including a plurality of primary input connectors each connectible to a primary power supply that supplies primary electrical energy, a redundancy power input connector connectible to a redundant power supply that supplies redundant electrical energy, a plurality of output connectors connectible to a display component powerable by the primary or redundant electrical energy, and a plurality of electrical pathways including primary pathways each connecting a primary input connector to a corresponding output connector, redundant pathways each connecting the redundancy input connector to a corresponding output connector.

Abstract: A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. In some embodiments, the cell is only read in response to an event. If in response to that reading, it is determined that the cell has changed state or resistance, it may deduce whether the change is a result of thermal exposure. Corrective measures may then be taken.

Abstract: A system comprises a redundancy circuit board including a plurality of primary input connectors each connectible to a primary power supply that supplies primary electrical energy, a redundancy power input connector connectible to a redundant power supply that supplies redundant electrical energy, a plurality of output connectors connectible to a display component powerable by the primary or redundant electrical energy, and a plurality of electrical pathways including primary pathways each connecting a primary input connector to a corresponding output connector, redundant pathways each connecting the redundancy input connector to a corresponding output connector.

Abstract: A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. In some embodiments, the cell is only read in response to an event. If in response to that reading, it is determined that the cell has changed state or resistance, it may deduce whether the change is a result of thermal exposure. Corrective measures may then be taken.

Abstract: A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. In some embodiments, the cell is only read in response to an event. If, in response to that reading, it is determined that the cell has changed state or resistance, it may deduce whether the change is a result of thermal exposure. Corrective measures may then be taken.

Abstract: A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. In some embodiments, the cell is only read in response to an event. If, in response to that reading, it is determined that the cell has changed state or resistance, it may deduce whether the change is a result of thermal exposure. Corrective measures may then be taken.

Abstract: A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. In some embodiments, the cell is only read in response to an event. If, in response to that reading, it is determined that the cell has changed state or resistance, it may deduce whether the change is a result of thermal exposure. Corrective measures may then be taken.

Abstract: A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. In some embodiments, the cell is only read in response to an event. If, in response to that reading, it is determined that the cell has changed state or resistance, it may deduce whether the change is a result of thermal exposure. Corrective measures may then be taken.

Abstract: Techniques related to magnetic latching are described herein. The techniques may include a first magnet formed in a curve, and a second magnet formed in the curve. A pole of the first magnet and a pole of the second magnet are directed inward toward a center line of the curve.

Abstract: Techniques related to magnetic latching are described herein. The techniques may include a first magnet formed in a curve, and a second magnet formed in the curve. A pole of the first magnet and a pole of the second magnet are directed inward toward a center line of the curve.

Abstract: A molding compound comprising a resin, a filler, and a carbon nano-tube dispersion is disclosed. The carbon nano-tube dispersion achieves a low average agglomeration size in the molding compound thereby providing desirable electromechanical properties and laser marking compatibility. A shallow laser mark may be formed in a mold cap with a maximum depth of less than 10 microns.

Abstract: Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, including a die and an encapsulant material formed over the die, and at least one topological feature formed on an external surface of the encapsulant material, and configured to resist out-of-plane deformation of the package. Other embodiments may be described and claimed.

Abstract: A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. In some embodiments, the cell is only read in response to an event. If, in response to that reading, it is determined that the cell has changed state or resistance, it may deduce whether the change is a result of thermal exposure. Corrective measures may then be taken.

Abstract: Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, including a die and an encapsulant material formed over the die, and at least one topological feature formed on an external surface of the encapsulant material, and configured to resist out-of-plane deformation of the package. Other embodiments may be described and claimed.

Abstract: A molding compound comprising a resin, a filler, and a carbon nano-tube dispersion is disclosed. The carbon nano-tube dispersion achieves a low average agglomeration size in the molding compound thereby providing desirable electromechanical properties and laser marking compatibility. A shallow laser mark may be formed in a mold cap with a maximum depth of less than 10 microns.

Abstract: An integrated circuit may be secured to a substrate using an anisotropically conductive adhesive that may be cured at a temperature of less than 150° C. In some embodiments, an acrylic resin with embedded metallic particles may be used as the anisotropically conductive adhesive. In some embodiments, the board level reliability of the resulting product may be improved through the use of the anisotropically conductive adhesive that may be cured at a temperature of less than 150° C.

Abstract: Numerous embodiments of variable latch and a method of formation are disclosed. One or more embodiments of the claimed subject matter may comprise a latch with a plurality of contact points formed thereon, and method of fabrication. The plurality of contact points may allow adequate socketing of microelectronic packages of varying sizes in a socket assembly, without the need to modify the latch when the microelectronic package size varies.