Patents by Inventor Jason Chung-Shih Chen

Jason Chung-Shih Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9202005
    Abstract: A design verification workstation contains both debug and constraint solver capabilities during simulation of a design under test. The design verification workstation is configured to allow the user to debug constraints, stop the constraint solver, navigate problems and variables, and make modifications on-the fly during the simulation to constraint information. Additionally, in some embodiments, the design verification workstation may allow a user to use a constraint solver to experiment if the modifications will lead to desired test stimulus. Since this debug process happens during simulation, users do not need to recompile the test case. Additionally, once a user is satisfied with the modifications made to the simulation, the modification could be saved for future usage.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: December 1, 2015
    Assignee: SYNOPSYS, INC.
    Inventors: Dhiraj Goswami, Aijun Hu, Na Xing, Jason Chung-Shih Chen, Ngai Ngai William Hung
  • Publication number: 20150067622
    Abstract: A design verification workstation contains both debug and constraint solver capabilities during simulation of a design under test. The design verification workstation is configured to allow the user to debug constraints, stop the constraint solver, navigate problems and variables, and make modifications on-the fly during the simulation to constraint information. Additionally, in some embodiments, the design verification workstation may allow a user to use a constraint solver to experiment if the modifications will lead to desired test stimulus. Since this debug process happens during simulation, users do not need to recompile the test case. Additionally, once a user is satisfied with the modifications made to the simulation, the modification could be saved for future usage.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 5, 2015
    Inventors: Dhiraj Goswami, Aijun Hu, Na Xing, Jason Chung-Shih Chen, Ngai Ngai William Hung
  • Patent number: 6823432
    Abstract: A method and apparatus for load distribution across memory banks with constrained access is accomplished using a bank balancer that ensures that data to be buffered is evenly distributed throughout the various banks of the memory structure. The bank balancer maintains bank depth information relating to each of the banks. The bank balancer receives dequeue and enqueue information, where the dequeue information specifies read operations that will remove data from the various banks, and the enqueue information indicates that there is data to be written to the memory banks. The dequeue information constrains which banks may be utilized to enqueue received data. In order to determine to which banks to enqueue data, the bank balancer sorts the banks by their depth. The bank balancer then eliminates those banks which cannot be used for enqueue operations due to either the dequeue operations or other enqueue operations that have already been determined.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: November 23, 2004
    Inventors: Jason Chung-Shih Chen, Paul M. Ruffle, Albert D. Heller
  • Publication number: 20030051108
    Abstract: A method and apparatus for load distribution across memory banks with constrained access is accomplished using a bank balancer that ensures that data to be buffered is evenly distributed throughout the various banks of the memory structure. The bank balancer maintains bank depth information relating to each of the banks. The bank balancer receives dequeue and enqueue information, where the dequeue information specifies read operations that will remove data from the various banks, and the enqueue information indicates that there is data to be written to the memory banks. The dequeue information constrains which banks may be utilized to enqueue received data. In order to determine to which banks to enqueue data, the bank balancer sorts the banks by their depth. The bank balancer then eliminates those banks which cannot be used for enqueue operations due to either the dequeue operations or other enqueue operations that have already been determined.
    Type: Application
    Filed: May 28, 2002
    Publication date: March 13, 2003
    Inventors: Jason Chung-Shih Chen, Paul M. Ruffle, Albert D. Heller
  • Patent number: 6415366
    Abstract: A method and apparatus for load distribution across memory banks with constrained access is accomplished using a bank balancer that ensures that data to be buffered is evenly distributed throughout the various banks of the memory structure. The bank balancer maintains bank depth information relating to each of the banks. The bank balancer receives dequeue and enqueue information, where the dequeue information specifies read operations that will remove data from the various banks, and the enqueue information indicates that there is data to be written to the memory banks. The dequeue information constrains which banks may be utilized to enqueue received data. In order to determine to which banks to enqueue data, the bank balancer sorts the banks by their depth. The bank balancer then eliminates those banks which cannot be used for enqueue operations due to either the dequeue operations or other enqueue operations that have already been determined.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: July 2, 2002
    Assignee: Alcatel Canada Inc.
    Inventors: Jason Chung-Shih Chen, Paul M. Ruffle, Albert D. Heller