Abstract: A method for designing a system on a target device is disclosed. Domains and sub-domains in the system are identified. A sub-domain is divided into a plurality of chunks. Slacks for the chunks are computed in parallel. Other embodiments are described and claimed.

Abstract: A method for reporting timing exception status is presented. The method begins by computing a set of edges of a sub-domain and a set of edges of a timing exception. A slack value is computed based on either the edges of the sub-domain common to the set of edges of the timing exception or the timing paths of the sub-domain. If the sub-domain has a valid slack value, the method compares the sub-domain timing exception type to the timing exception type of the timing exception. The method identifies the timing exception as being overridden if both timing exception types are different and either the slack value computed based on edges of the sub-domain is valid, or the sub-domain has the valid slack value and an intersection of the set of edges of the sub-domain and of the timing exception forms a timing path. The method presents the overridden timing exceptions.

Abstract: A method for designing a system on a target device is disclosed. Domains and sub-domains in the system are identified. Chunks are identified from the domains and sub-domain. Slacks for the chunks are computed in parallel. Other embodiments are described and claimed.

Abstract: The present invention is directed to clock domain conflict analysis of a timing graph that features, dissociating clock domains of one or more of a path having conflicting clock domains while preserving the original clock domain relationship of the edges in the path. To that end, the method includes generating a timing graph having a source instance, a destination instance and a plurality of edges defining a plurality of signal paths between the source instance and the destination instance. A plurality of clock domains is corresponded to the timing graph, with a subset of the plurality of edges being associated with more than one clock domain. From the subset, conflicting clock domains associated with a common edge are identified. In response to identification of the conflict, one of the clock domains is dissociated from one of the edges of the subset.

Abstract: A method for designing a system on a target device includes merging a post-fit netlist for a first partition of the system from a set-up compilation with a post-synthesis netlist for a second partition of the system from an incremental compilation to form a combined netlist. Fitting is performed on the combined netlist.